A 60-GHz CMOS Transmit/Receive Switch
Chien M. Ta, Efstratios Skafidas, and Robin J. Evans
National ICT Australia (NICTA)
Department of Electrical and Electronic Engineering
University of Melbourne
Parkville, VIC 3010
Abstract—A single-pole double-throw (SPDT) transmit/receive
switch (T/R switch) operating in the 57–66 GHz band is imple-
mented on a 130-nm CMOS process. The switch exhibits an
insertion loss from 4.5 dB to 5.8 dB, an isolation from 24.1 dB
to 26 dB, a return loss at antenna port from -9.2 dB to -10.5 dB,
and a return loss at Tx/Rx port below -15 dB for the frequency
band. With a control voltage of 1.2 V the IP1dB of the switch is
4.1 dBm. The switch features fast switching speed with rise-time
and fall-time of 400 ps and 360 ps, respectively. This is the first
CMOS T/R switch designed for very short range radio in 60-GHz
The 60-GHz band has been released for unlicensed use as
a response to the demand of broadband wireless communica-
tions . The short wavelength at 60 GHz makes it possible to
integrate the antennas and the RF transceiver on a single die.
A T/R switch can be employed so that a single antenna can be
shared between the transmitter and the receiver to save area
and cost of the chip. Even if an off-chip antenna is desired,
an integrated T/R switch can still be used to reduce cost.
CMOS T/R switches have been designed at 5.2 GHz and
15 GHz –. However, at millimeter-wave frequencies, the
design of silicon-based T/R switches becomes much more
challenging due to the coupling of the RF signals to the semi-
conductive silicon substrate. Firstly, insertion loss is increased
because of signal loss in the substrate. Secondly, isolation
is decreased as a result of resistive coupling through the
substrate. Apart from the detrimental effects of the silicon
substrate, the low control voltage that accompanies deep sub-
micron CMOS technology limits the power handling capability
of the switch.
In this paper, the design of a T/R switch on a 130-nm CMOS
process targeting 57-66 GHz band is presented. The control
voltages of the switch are 0 V and 1.2 V so that the T/R switch
can be driven directly by digital circuitry. Trade-offs among
key design parameters, insertion loss, isolation, and power
handling capability, under low control voltage constraint and
high frequency operation requirement are studied and applied
to the design.
This paper consists of four sections, beginning with this
introduction. The design of the T/R switch is covered in
Section II. Measurement results are presented and discussed
in Section III. Finally, this work is summarized in Section IV.
II. CIRCUIT DESIGN
Key design specifications for a T/R switch are insertion
loss, isolation, and power handling capability (IP1dB). With the
provision that high isolation is difficult to achieve at 60 GHz, a
shunt-series SPDT architecture was chosen for the switch. The
final topology of the T/R switch, as shown in Fig. 1, includes a
SPDT switching core and three impedance matching networks
corresponding to three RF ports.
Fig. 1.Topology of the shunt-series SPDT switch.
A. Design of the SPDT core
The SPDT core is built upon several MOS transistor
switches. In this section the trade-offs in the design of a MOS
transistor switch are presented.
Models of a MOS transistor biased in deep triode region,
corresponding to the ON state of the switch, and cut-off
region, corresponding to the OFF state of the switch, are
shown in Fig. 2(a) and (b), respectively. The insertion loss
of a MOS transistor switch under the ON state is dominated
by its on-resistance, Ron, and substrate resistance, Rb .
Isolation of the switch under the OFF state is finite due to
signal coupling through the parasitic capacitances, Cds, Cgs,
and Cgd, and through the junction capacitances, Csband Cdb.
The power handling capability of the switch is limited due
to the unintentional turning on of the source/drain-to-substrate
junction diodes . In Fig. 2 these diodes are represented by
their junction capacitances, Csband Cdb.
and (b) OFF state.
Models of a MOS transistor operating as a switch in (a) ON state
The on-resistance is given by 
To reduce the insertion loss it is desired to keep Ron small.
This can be achieved by:
• Choosing transistor with large µ;
• Increasing W/L;
• Keeping Vgs− VTHlarge.
The first criterion suggests using NMOS transistors rather than
PMOS transistors in the design. The second measure suggests
the use of transistors with minimum allowable channel length.
Because the minimum value of L is limited by the technology,
low Ron eventually requires large W. However, widening a
transistor will increase its junction and parasitic capacitances
proportionally. There are several consequences of this effect.
When the transistor is ON, increasing Csb and Cdb leads to
more signal being coupled to the substrate and dissipated in the
substrate resistance Rb. When the transistor is OFF, increasing
Cds, Cgd, and Cgsleads to lower isolation between the source
and drain due to capacitive coupling between these terminals.
It is interesting to examine the fundamental difference
between the design of MOS transistor switches at 60-GHz
band as compared to frequencies of 15 GHz and below.
For low frequency designs, isolation is not a parameter that
is optimized during the design process because adequate
isolation can be obtained at low frequencies. Thus, in these
designs, only insertion loss needs to be minimized. No trade-
off between insertion loss and isolation is required. On the
other hand, at 60 GHz, isolation is smaller due to several
low impedance paths caused by parasitic capacitances. This
necessitates a trade-off between insertion loss and isolation
during sizing the transistors.
Apart from shrinking the transistor size, another measure
to reduce the junction capacitances is to exploit their bias-
dependent nature which is formulated as 
Area × Cj0
(1 + VR/ΦB)mj+Perimeter × Cjsw0
(1 + VR/ΦBsw)mjsw
where VRis Vsbor Vdb, ΦB and ΦBsware the junction and
sidewall built-in potentials, Cj0and Cjsw0are the capacitance
per unit area and unit length of the junction and the sidewall
when VR = 0. This expression signifies that by biasing the
source/drain to a higher voltage, smaller junction capacitances
can be obtained. In addition, as described in , positively
biasing the source/drain also increases the power handling
capability of the switch. However, when Vdand Vsincrease,
two more effects take place concurrently: (a) Vgs decreases,
and (b) VTHincreases because
where γ is the body effect coefficient and ΦF is the Fermi
level in the substrate. The simultaneous reduction in Vgsand
increase in VTH result in smaller Vgs− VTH. This leads
to higher Ron according to (1). In conclusion, by increasing
the source/drain voltage we sacrifice insertion loss for power
Taking into account the effects of sizing and biasing on
insertion loss, isolation, and power handling capability, the
SPDT core was designed as follows. The source/drain of
all transistors were biased to 0 V to keep Ron low. This
was at the expense of low power handling capability. This
trade-off is required here because the control voltage (Vg)
is limited to 1.2 V and power requirements are low for
short range communications. The main switching transistors,
M1 and M2, are sized to provide low on-resistance whilst
presenting moderate junction capacitances. Low capacitance
is necessary to keep the Q factor of the circuit low which
allows wideband matching to a 50 Ω source/load. Low Q
circuits are also less sensitive to parasitic capacitances and
process variations. The transistors M3and M4are introduced
to increase the isolation of the switch even though they do
introduce additional capacitances and losses at nodes x and y
in Fig. 1. The sizes of the transistor are also shown in Fig. 1.
The gates of all transistors are biased through large resistors
(10 kΩ) which make the gate terminals appear to be open to
AC signals. Thus, no power loss occurs at the gate terminals.
VTH= VTH0+ γ
|2ΦF+ Vsb| −
B. Design of the impedance matching networks
The low input impedance at nodes x, y, and z in Fig. 1 are
transformed to 50 Ω by LC impedance matching networks.
The series inductors of these LC networks are realized by
transmission lines (TML1–3). The capacitors of these LC
networks are implemented as a finger metal capacitor, CM,
at the antenna port and as junction capacitances (of M5and
M6) at Tx and Rx ports. The shunt transistors M5and M6are
used because high isolation is desired in this design. They can
be replaced by MIM capacitors to improve the power handling
capability of the switch in other designs.
Finally, metal-insulator-metal (MIM) capacitors are used
for AC coupling at all three RF ports. The bottom-plate
parasitic capacitance of these capacitors are absorbed into
the matching networks to mitigate the non-linearity of the
junction capacitances at nodes x1and y1. By using on-chip DC
blocking capacitors, the T/R switch is completely integrated
and can operate without any off-chip components.
C. Layout considerations
In the small-signal models in Fig. 2 it is assumed that the
gate of the MOS transistor is biased through a very large
resistor which basically makes the gate terminal open to AC
signals. To preserve the effectiveness of Rg, special attention
has been made to keep Cgbsmall as this parasitic capacitance
is in parallel with Rg.
Transmission lines are implemented in microstrip form with
the signal line on the top metal layer and ground on the lowest
metal layer (M1). The ground plane of the microstrip helps
minimize electric field from penetrating into the substrate
and introducing losses. Other signal-bearing metal such as
connections and RF pads are also shielded from the lossy
substrate by the M1 ground-plane. Substrate shield techniques
 are employed throughout the design to reduce substrate
coupling and create well-defined parasitic capacitances that
can be predicted by extraction tools.
III. EXPERIMENTAL RESULTS AND DISCUSSION
The design is realized in a commercially available RF
CMOS technology which features thick metal layers that
can be used to implement high-Q inductors, capacitors, and
transmission lines. Fig. 3 is a microphotograph of the T/R
switch. The layout (without test pads) occupies an area of
680 µm × 325 µm. A summary of the performance of the
T/R switch is given in Table I.
(excluding pads) is 680 µm × 325 µm.
Chip microphotograph. Layout dimension of the T/R switch
A. Small-signal performance
S-parameters up to 65 GHz were measured on-wafer and de-
embedded. The results are shown in Fig. 4. Return loss at Tx
port, S11, is from -15 dB to -26 dB. Return loss at antenna
port, S22, is from from -9.2 dB to -10.5 dB. Insertion loss
measured between Tx port and antenna port varies between
4.5 dB and 5.8 dB. This high insertion loss is due to loss in
the silicon substrate as mentioned previously. Although this
insertion loss is higher than that of discrete T/R switches in
GaAs , for discrete components, additional losses associated
SUMMARY OF THE PERFORMANCE OF THE T/R SWITCH
Return loss at Tx/Rx port
Return loss at antenna port
57 GHz to 66 GHz
1.2 V / 0 V
4.5 dB to 5.8 dB
24.1 dB to 26 dB
−15 dB to −27 dB
−9.2 dB to −10.5 dB
with cables and connectors, which are quite high at 60 GHz,
must be taken into account in the system implementation.
Isolation measured between the Tx port and the Rx port is
from 24.1 dB to 26 dB which is comparable to the level of
isolation offered by discrete switches .
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Fig. 4.Measured S-parameters.
B. Power handling capability
At 60 GHz, the T/R switch starts to compress at 4.1 dBm
input power as shown in Fig. 5. This low IP1dB is due to
the fact that the control voltage is low (only 1.2 V) and the
sources/drains of the transistors are biased to ground . By
using a higher control voltage and biasing the sources/drains
of the transistors to higher potential, higher power handling
capability can be achieved.
C. Switching speed
The switching speed of the T/R switch is characterized by
the rise time, trise, and fall time, tfall. A simulation result
to decide the switching speed is shown in Fig. 6. In this
simulation, the control voltages are 50% duty pulses with a
high level of 1.2 V and a low level of 0 V, the input signal
is a sinusoid waveform at 60 GHz at -3 dBm. The rise time
(from 10% to 90% of maximum output swing) and fall time
(90% down-to 10% of maximum output swing) are 400 ps
−20 −15−10 −505 10 Download full-text
Input power (dBm)
Output power (dBm)
Fig. 5.Measured power handling capability of the switch. IP1dBis 4.1 dBm
and 360 ps, respectively. This fast switching speed is possible
owing to the small switching transistors. This sub-nanosecond
switching speed is much faster than the speed of GaAs switch
operating at GHz frequencies which is usually on the order of
tens of nanoseconds . The switching speed can be improved
futher by decreasing the values of the gate resistors as long as
the resistors are still large enough to make the gates open to
Fig. 6. Simulation of switch’s speed using a 200-MHz 50% duty pulse. Rise
time and fall time are 400 ps and 360 ps, respectively.
D. Figure of merit (FOM)
The FOM recommended in , was used for comparing
this work to other works.
× Isolation × P1dB
A summary of the comparison is shown in Table II. The T/R
switch in this work has the best FOM among T/R switches of
symmetrical types which do not optimized transmitting path
and receiving path separately.
IV. CONCLUSION REMARKS AND FUTURE WORKS
The design of a T/R switch in a low-cost CMOS technology
for 57-66 GHz band has been presented. The switch exhibits
good matching and isolation. The insertion loss and power
handling capability of the switch can be improved by using
a higher control voltage. The presented switch is suitable for
short range wireless communications where power handling
requirements are not very high.
The authors would like to thank National ICT Australia for
supporting this work and Mr. Byron Wicks for reviewing this
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