Conference Paper

A 60-GHz CMOS transmit/receive switch

Univ. of Melbourne, Parkville
DOI: 10.1109/RFIC.2007.380985 Conference: Radio Frequency Integrated Circuits (RFIC) Symposium, 2007 IEEE
Source: IEEE Xplore


A single-pole double-throw (SPDT) transmit/receive switch (T/R switch) operating in the 57-66 GHz band is implemented on a 130-nm CMOS process. The switch exhibits an insertion loss from 4.5 dB to 5.8 dB, an isolation from 24.1 dB to 26 dB, a return loss at antenna port from -9.2 dB to -10.5 dB, and a return loss at Tx/Rx port below -15 dB for the frequency band. With a control voltage of 1.2 V the IP1dB of the switch is 4.1 dBm. The switch features fast switching speed with rise-time and fall-time of 400 ps and 360 ps, respectively. This is the first CMOS T/R switch designed for very short range radio in 60-GHz band.

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Available from: Stan Skafidas, Oct 05, 2015
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    • "However, in CMOS technology, the maximum unity current gain frequency is much lower than that of bipolar technology. Therefore, developing the transceiver working at 77 GHz in CMOS is very challenging [9]–[11]. With the motivation to develop a low-cost high-integration radar transceiver, this paper presents a design of a CMOS receiver (Rx) front-end operating in the 76–77-GHz band. "
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    ABSTRACT: This paper presents the design of a receiver (Rx) front-end for automotive radar application operating at 76-77 GHz. The Rx employs a double conversion architecture, which consists of a five-stage low-noise amplifier (LNA), a sub-harmonic mixer (SHM), and a double-balanced passive mixer (PSM). By adopting this architecture, millimeter-wave frequency synthesizer design can be relaxed. In the LNA layout, the output of each stage is positioned close to the input of the follow stage, thus creating a LC resonance load. As a result, complex interstage matching networks is simplified. The SHM driven by a 38-GHz local oscillator (LO) is adopted to avoid push/pull effect and power consumption of the voltage-controlled oscillator. A PSM is utilized for the second conversion since it consumes no dc current and has low flickering noise. To connect the singled-ended LNA and SHM, a 77-GHz balun is designed; and for driving the SHM, two 38-GHz baluns and an in-phase/quadrature coupler to provide quadrature 38-GHz LO are designed. The proposed Rx is implemented in a 65-nm CMOS technology and measurement results show 16-dB voltage gain and 13-dB calculated noise figure while dissipating 23.5 mA from a black 1.2-V supply.
    IEEE Transactions on Microwave Theory and Techniques 10/2013; 61(10):3783-3793. DOI:10.1109/TMTT.2013.2279368 · 2.24 Impact Factor
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    • "In [10], the LC-tuned technique is used to form a CMOS SPDT switch to reduce the effect of the parasitic capacitance, but it only achieves a very narrow bandwidth. The transmission-line integrated switches demonstrate good performance in MMW frequency [8], [11]. Manuscript received July 26, 2009; revised October 28, 2009. "
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    ABSTRACT: This letter demonstrates a fully integrated transmit/receive single-pole-double-throw switch in standard bulk 90 nm CMOS process. This switch is based on the transmission-line integrated approach that reduces the effect of parasitic capacitance of transistors in the desired band, and this approach can achieve good isolation and return loss with fewer stages of transistors and broad bandwidth. The switch provides an insertion loss of 3-4 dB and a return loss better than 10 dB in 60-110 GHz. The measured isolation is better than 25 dB. The measured 1 dB compression point of input power is 10.5 dBm at 75 GHz. To the best of our knowledge, this is the first CMOS switch operating beyond 100 GHz.
    IEEE Microwave and Wireless Components Letters 03/2010; 20(2-20):85 - 87. DOI:10.1109/LMWC.2009.2038519 · 1.70 Impact Factor
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    • "This criterion of reducing R on can be achieved by using n-MOSFET transistors in place of p-MOSFET transistors in the design [22] "
    Wireless Engineering and Technology 01/2010; 1(02):47-54. DOI:10.4236/wet.2010.12008
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