Implementation of a Low-Complexity Frame-Start Detection Algorithm for MIMO Systems
ABSTRACT Multiple-input multiple-output (MIMO) communication systems require well-designed synchronization schemes in the receiver to meet stringent QoS requirements. In particular, OFDM modulation is very sensitive to timing synchronization errors, which cause inter-symbol interference. This paper describes a frame-start detection algorithm, which relies on received signal power increase and does not require any special properties of the transmitted signal. The performance is analyzed and then, verified through simulations in a MIMO system employing orthogonal frequency division multiplexing. Finally, a low-complexity FPGA implementation of the presented algorithm is described in detail.
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ABSTRACT: The performance of an FPGA-based MIMO-OFDM testbed is investigated through measurements. The setup includes two real-time terminals, supporting up to 4 spatial streams, and a wideband multipath channel emulator. The per-formance of the system, transmitting at data rates up to 216 Mbit/s over a 20 MHz channel in the 2.4 GHz ISM band, is benchmarked under different channel scenarios. The im-pact of different algorithm choices at the receiver, includ-ing parameter estimation for synchronization and channel estimation, on system-level performance is also evaluated. The FPGA implementation results for the different PHY-layer subsystems provide relevant insight into possible tradeoffs between performance and silicon complexity.
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ABSTRACT: When designing complex communication systems, such as MIMO-OFDM transceivers, prototypes have become an important tool for understanding the implementation trade-offs and the system behavior. This paper presents a real-time FPGA prototype for a 4-stream MIMO-OFDM transceiver capable of transmitting 216 Mbit/s in 20 MHz bandwidth. The paper covers all parts of the system from RF to channel decoding and considers both algorithm and implementation aspects. In particular, we discuss the initial parameter estimation, channel estimation, MIMO detection, parameter tracking, and channel decoding. FPGA implementation results are reported along with measurements that demonstrate the throughput of spatial multiplexing with four spatial streams.IEEE Journal on Selected Areas in Communications 09/2008; · 3.12 Impact Factor
Conference Paper: Multi-user MIMO testbed.[Show abstract] [Hide abstract]
ABSTRACT: This paper provides an overview of a real-time multi-user multiple-input multiple-output (MIMO) communication testbed designed for demonstration and assessment of real-world wireless communication aspects. The testbed is built on a modular hardware platform consisting of three different boards and incorporates a MIMO-OFDM-based physical (PHY) layer, an embedded media access controller (MAC), and an Ethernet interface. Due to the modular design of the testbed, it can be used for both, real-time and offline processing experiments with real-world aspects.Proceedings of the Third ACM Workshop on Wireless Network Testbeds, Experimental Evaluation and Characterization, WINTECH 2008, San Francisco, California, USA, September 19, 2008; 01/2008