Conference Paper
MultiVth Level Conversion Circuits for MultiVDD Systems
Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI
DOI: 10.1109/ISCAS.2007.378489 Conference: Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on Source: IEEE Xplore

Conference Paper: An efficient dualsupply design for lowpower mobile systems
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ABSTRACT: This paper overviews dualsupply design for lowpower mobile systems in deep submicron technology. Various dualsupply design schemes were investigated for real world design in terms of power efficiency. The analysis showed that a dualsupply design applied to a clock network was more efficient than that applied to datapath logics. For example, the dualsupply clock network with clockgating level converter can minimize the penalties of level conversion in terms of power, area, and performance. It can also achieve higher operating frequency due to the mitigated timing constraint on gated clocks. Frequency doubling readily derived from existing level converters can save more power by halving the clock frequency. Furthermore, the clockgating level converter can enable a system to exploit pulsebased flipflops without pulse generators, resulting in more power reduction.SoC Design Conference (ISOCC), 2012 International; 01/2012 
Article: Parametric yield driven resource binding in behavioral synthesis with multi V th /V dd library
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ABSTRACT: The everincreasing chip power dissipation in SoCs has imposed great challenges on today's circuit design. It has been shown that multiple threshold and supply voltages assignment (multiVth/Vdd) is an effective way to reduce power dissipation. However, most of the prior multiVth/Vdd optimizations are performed under deterministic conditions. With the increasing process variability that has significant impact on both the power dissipation and performance of circuit designs, it is necessary to employ statistical approaches in analysis and optimizations for low power. This paper studies the impact of process variations on the multiVth/Vdd technique at the behavioral synthesis level. A multiVth/Vdd resource library is characterized for delay and power variations at different voltage combinations. A parametric yielddriven resource binding algorithm is then proposed, which uses the characterized power and delay distributions and efficiently maximizes power yield under a timing yield constraint. During the resource binding process, voltage level converters are inserted between resources when required. Experimental results show that significant power reduction can be achieved with the proposed variationaware framework, compared with traditional worstcase based deterministic approaches.01/2010; 
Conference Paper: Bidirectional SingleSupply Level Shifter with Wide Voltage Range for Efficient Power Management
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ABSTRACT: Level shifter circuits are used to interface multiple voltage islands in many modern ICs or SystemsonChip (SoCs). Singlesupply level shifters are being used to reduce the power routing resources and minimize the routing congestion at the chip level. A singlesupply bidirectional level shifter aimed at low voltage which offers a wide voltage range (SSWVRLS) is designed using standard commercial 90nm CMOS process. The proposed level shifter uses analog and digital circuit techniques to provide full voltage shifting range for any combination of supply voltages (VDDIN = VDD,VDDIN ; VDD) in any step size (paper shows 25mv step) with no requirement for special lowVτ or highVτ devices, thus reducing the process cost. Post layout SPICE simulation comparison results show that proposed circuit is functional for full core supply voltage range (0.6V  1.32V) compared to other published level shifters. The circuit was tested for robustness under process mismatch conditions by 1000 point global and local Monte Carlo simulations.VLSI Design (VLSID), 2012 25th International Conference on; 01/2012
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