Conference Paper

Multi-Vth Level Conversion Circuits for Multi-VDD Systems

Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI
DOI: 10.1109/ISCAS.2007.378489 Conference: Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Source: IEEE Xplore

ABSTRACT Employing multiple supply voltages (multi-VDD) is attractive for reducing the power consumption without sacrificing the speed of an integrated circuit (IC). In order to transfer signals among the circuits operating at different voltage levels specialized voltage interface circuits are required. Two novel multi-threshold voltage (multi-Vth) level converters are proposed in this paper. The proposed level converters are compared with the previously published circuits for different values of the lower supply voltage. When the circuits are individually optimized for minimum power consumption in a 0.18mum CMOS technology, the proposed level converters offer significant power savings of up to 70% as compared to the previously published circuits. Alternatively, when the circuits are individually optimized for minimum propagation delay, speed is enhanced by up to 78% with the proposed circuits.

  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper overviews dual-supply design for low-power mobile systems in deep sub-micron technology. Various dual-supply design schemes were investigated for real world design in terms of power efficiency. The analysis showed that a dual-supply design applied to a clock network was more efficient than that applied to data-path logics. For example, the dual-supply clock network with clock-gating level converter can minimize the penalties of level conversion in terms of power, area, and performance. It can also achieve higher operating frequency due to the mitigated timing constraint on gated clocks. Frequency doubling readily derived from existing level converters can save more power by halving the clock frequency. Furthermore, the clock-gating level converter can enable a system to exploit pulse-based flip-flops without pulse generators, resulting in more power reduction.
    SoC Design Conference (ISOCC), 2012 International; 01/2012
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: The ever-increasing chip power dissipation in SoCs has imposed great challenges on today's circuit design. It has been shown that multiple threshold and supply voltages assignment (multi-Vth/Vdd) is an effective way to reduce power dissipation. However, most of the prior multi-Vth/Vdd optimizations are performed under deterministic conditions. With the increasing process variability that has significant impact on both the power dissipation and performance of circuit designs, it is necessary to employ statistical approaches in analysis and optimizations for low power. This paper studies the impact of process variations on the multi-Vth/Vdd technique at the behavioral synthesis level. A multi-Vth/Vdd resource library is characterized for delay and power variations at different voltage combinations. A parametric yield-driven resource binding algorithm is then proposed, which uses the characterized power and delay distributions and efficiently maximizes power yield under a timing yield constraint. During the resource binding process, voltage level converters are inserted between resources when required. Experimental results show that significant power reduction can be achieved with the proposed variation-aware framework, compared with traditional worst-case based deterministic approaches.
  • [Show abstract] [Hide abstract]
    ABSTRACT: Level shifter circuits are used to interface multiple voltage islands in many modern ICs or Systems-on-Chip (SoCs). Single-supply level shifters are being used to reduce the power routing resources and minimize the routing congestion at the chip level. A single-supply bidirectional level shifter aimed at low voltage which offers a wide voltage range (SS-WVRLS) is designed using standard commercial 90nm CMOS process. The proposed level shifter uses analog and digital circuit techniques to provide full voltage shifting range for any combination of supply voltages (VDDIN = VDD,VDDIN ; VDD) in any step size (paper shows 25mv step) with no requirement for special low-Vτ or high-Vτ devices, thus reducing the process cost. Post layout SPICE simulation comparison results show that proposed circuit is functional for full core supply voltage range (0.6V - 1.32V) compared to other published level shifters. The circuit was tested for robustness under process mismatch conditions by 1000 point global and local Monte Carlo simulations.
    VLSI Design (VLSID), 2012 25th International Conference on; 01/2012

Full-text (3 Sources)

1 Download
Available from
Feb 18, 2015