Conference Proceeding

Flexible Ultra Low Power Successive Approximation Analog-to-Digital Converter with Asynchronous Clock Generator

Univ. of Neuchatel, Neuchatel
Canadian Conference on Electrical and Computer Engineering 05/2007; DOI:10.1109/CCECE.2007.412 pp.1649 - 1652 In proceeding of: Electrical and Computer Engineering, 2007. CCECE 2007. Canadian Conference on
Source: IEEE Xplore

ABSTRACT An ultra low power 8-bit current-mode successive approximation (SAR) analog-to-digital (ADC) converter for wireless sensor network (WSN) applications is presented. The proposed ADC contains a new asynchronous clock generator, which works only during data processing and is turned off afterwards, thus enabling a power saving mode. The clock generator is controlled by a bias current, and can be adjusted for a wide range of sampling frequencies. The proposed ADC with the clock generator occupy a chip area of 3500 mum2 and dissipate 400 nW power from a 0.6 V supply voltage in a CMOS 0.18-mum technology, enabling input data processing with a frequency of 100 kHz.

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Keywords

bias current
 
clock generator
 
new asynchronous clock generator
 
proposed ADC
 
sampling frequencies
 
supply voltage
 
ultra low power 8-bit current-mode successive approximation
 
wide range
 
wireless sensor network