Compensation Circuit Design Considerations for high Frequency DC/DC Buck Converters with Ceramic Output Capacitors
ABSTRACT Modern power applications are driving the demand for power supply systems with fast transient response. This requires high bandwidth in addition to a robust system. The latest technology allows designing very high switching frequency (in the MHz range) DC-DC converters using ceramic capacitors as an output filter. Using traditional linear control will limit the maximum achievable bandwidth, and using the recently proposed non-linear control circuits will make the control circuit more complex and not as robust. This paper introduces loop compensation circuit design methods suitable for DC-DC converters operating at high switching frequencies (FSW > 1MHz), which are higher than the output capacitor's resonant frequency (FR Â¿ 1-2MHz). These developments are introduced in the context of the design and experimental evaluation of a 5 MHz DC-DC Buck converter. Special emphasis is placed on key design compensation circuits using the Error Amplifier as an active element in addition to the passive elements that are combined to present an improved novel active linear control scheme.
Conference Proceeding: Design methodology for dynamic voltage scaling in the buck converter[show abstract] [hide abstract]
ABSTRACT: Dynamic voltage scaling is a technique that reduces the energy consumption in electronics systems. This paper deals with the design of the buck converter to meet dynamic voltage specifications and regulation under load current steps. A design methodology is proposed. Filter designs, number of interleaved phases, optimum switching frequency and control speed are key parameters that are taken into account in this methodology. The minimum time control law enables the maximum inductance design at the optimum switching frequency, thus, maximizing the efficiency of the converter. This methodology is applied to a particular specification for dynamic voltage scaling and a prototype is built to validate the conceptsApplied Power Electronics Conference and Exposition, 2005. APEC 2005. Twentieth Annual IEEE; 04/2005
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ABSTRACT: This paper discusses the presence of steady-state limit cycles in digitally controlled pulse-width modulation (PWM) converters, and suggests conditions on the control law and the quantization resolution for their elimination. It then introduces single-phase and multi-phase controlled digital dither as a means of increasing the effective resolution of digital PWM (DPWM) modules, allowing for the use of low resolution DPWM units in high regulation accuracy applications. Bounds on the number of bits of dither that can be used in a particular converter are derived. Finally, experimental results confirming the theoretical analysis are presented.IEEE Transactions on Power Electronics 02/2003; · 4.08 Impact Factor
Conference Proceeding: Fast transient response with combined linear-non-linear control applied to buck converters[show abstract] [hide abstract]
ABSTRACT: Nowadays, one of the main challenges for power supplies designers is to feed the latest generation of microprocessors and DSPs, since they require high current slew rates together with low output voltage. In this paper, a novel control technique is presented to help the designers to comply with the current requirements. The proposed combined linear-nonlinear control (LnLC) scheme increases significantly the capability of conventional linear control to reduce the recovery time of the output voltage drop produced when a load current step occurs. Experimental results have been obtained for two cases: a synchronous rectifier buck converter, with a conventional voltage loop and the same converter with the novel LnLC. The comparison of these experimental results shows that, with the new control, the recovery time of the output voltage is reducedPower Electronics Specialists Conference, 2002. pesc 02. 2002 IEEE 33rd Annual; 02/2002