Structured Interleavers and Decoder Architectures for Zigzag Codes
ABSTRACT We propose structured interleaver design for parallel concatenated Zigzag codes. While the proposed design performs as good as or better than random interleavers for various block-sizes, it improves the error floor of the Zigzag codes and offers a lot of parallelism suitable for high data-rate applications. The interleaver can be specified with only a few parameters and can be efficiently implemented in both hardware and software. We also evaluate semi-parallel Zigzag decoder architecture that exploits the parallelism of the proposed interleavers to improve the throughput. We also evaluate the performance of an efficient decoding schedule for semi-parallel Zigzag decoder that provides better throughput and performance trade-offs compared to the fully parallel and serial decoder schedule. The proposed interleaver scheme and architecture are suitable for high throughput Ultra Wideband communications that demand data-rates up to several hundred mbps.