Conference Paper

Extraction of Power Dissipation Profile in an IC Chip from Temperature Map

Department of Electrical Engineering , University of California, Santa Cruz, Santa Cruz, California, United States
DOI: 10.1109/STHERM.2007.352405 Conference: Semiconductor Thermal Measurement and Management Symposium, 2007. SEMI-THERM 2007. Twenty Third Annual IEEE
Source: IEEE Xplore


This paper presents a new technique to calculate the power dissipation profile from the IC temperature map using an analogy with image processing and restoration. In this technique, finite element analysis (FEA) is used to find the heat point spread function of the IC chip. Then, the temperature map is used as input for an efficient image restoration algorithm which locates the sources of strong power dissipation non-uniformities. Therefore, for the first time the inverse heat transfer problem was optimally solved, and estimate the IC power map without involving extensive laboratory experiments. This computationally efficient and robust method, unlike some previous techniques in the literature, is applicable to virtually any experimental scenario. Simulation results on a typical commercial IC device confirm the effectiveness of our proposed method.

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    • "The work in [7] proposes to derive power maps from thermal maps with image processing algorithms. Finite element simulations are still required and iterative solvers are needed. "
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    ABSTRACT: Accurate power maps are useful for power model validation, process variation characterization, leakage estimation, and power optimization, but are hard to measure directly. Deriving power maps from measured thermal maps is the inverse problem of the power-to-temperature mapping, extensively studied through thermal simulation. Until recently this inverse heat conduction problem has received little attention in the microarchitecture research community. This paper first identifies the source of difficulties for the problem. The inverse mapping is then performed by applying constraints from microarchitecture-level observations. The inherent large sensitivity of the resultant power map is minimized through thermal map-filtering and constrained least-squares optimization. Choices of filter parameters and optimization constraints are investigated and their effects are evaluated. Furthermore, the paper highlights the differences between the grid and block modeling in the inverse mapping which were often ignored by previous schemes. The proposed methods reduce the mapping error by more than 10× compared to unoptimized solutions. To our best knowledge this is the first work to quantitatively evaluate and minimize the noise effect in the temperature to power mapping problem at the microarchitecture level for both grid and block mode, and for the steady and transient case.
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    ABSTRACT: This research program is aimed at developing a broad suite of techniques in detection, estimation, and reconstruction from images and video, which will help to advance the state of the art in automatic target recognition.
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    ABSTRACT: Static and dynamic hot spots limit the performance and reliability of electronic devices and ICs. We show that transient thermoreflectance imaging using a CCD camera can measure temperature distribution in chips with 0.1°C temperature, 100 nanosecond time, and submicron spatial resolution. It is possible to measure the temperature on metal interconnects in wire-bonded chips and, with through-the-substrate infrared illumination, at the transistor level in flip-chip packages. Recent results in transient thermal imaging of GaN transistors, ESD protection devices, solar cells, and LEDs are presented. We show it is possible to identify non-uniform temperature rise and defects in 200 to 300 nm interconnect vias that have been stressed at high temperatures. Power blurring techniques can be used to obtain transient temperature profiles in packaged IC chips with a calculation time orders of magnitude faster than finite element analysis. The technique is well suited to solve the inverse problem and extract the power dissipation profile from the measured thermal map.
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