Conference Proceeding

Enhanced code density of embedded CISC processors with echo technology

10/2005; DOI:10.1145/1084834.1084878 pp.160 - 165 In proceeding of: Hardware/Software Codesign and System Synthesis, 2005. CODES+ISSS '05. Third IEEE/ACM/IFIP International Conference on
Source: IEEE Xplore

ABSTRACT Code density is an important issue in memory constrained systems. Some RISC processor, e.g. the THUMB extension in the ARM processor, supports aggressive code size reduction even at the cost of significant performance loss. In this paper, we develop an algorithm that utilizes a set of novel variable length Echo instructions and evaluate its effectiveness for IA32 binaries. Our experiments show that IA32 processor equipped with Echo instructions is capable of achieving a similar code density as the THUMB extension in the ARM instruction set with significantly lower performance penalty.

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    Conference Proceeding: Code density concerns for new architectures
    V.M. Weaver, S.A. McKee
    [show abstract] [hide abstract]
    ABSTRACT: Reducing a program's instruction count can improve cache behavior and bandwidth utilization, lower power consumption, and increase overall performance. Nonetheless, code density is an often overlooked feature in studying processor architectures. We hand-optimize an assembly language embedded benchmark for size on 21 different instruction set architectures, finding up to a factor of three difference in code sizes from ISA alone. We find that the architectural features that contribute most heavily to code density are instruction length, number of registers, availability of a zero register, bit-width, hardware divide units, number of instruction operands, and the availability of unaligned loads and stores. We extend our results to investigate operating system, compiler, and system library effects on code density. We find that the executable starting address, executable format, and system call interface all affect program size. While ISA effects are important, the efficiency of the entire system stack must be taken into account when developing a new dense instruction set architecture.
    Computer Design, 2009. ICCD 2009. IEEE International Conference on; 11/2009
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Keywords

aggressive code size reduction
 
algorithm
 
ARM instruction
 
ARM processor
 
Echo instructions
 
IA32 binaries
 
IA32 processor
 
lower performance penalty
 
novel variable length Echo instructions
 
RISC processor
 
significant performance loss
 
THUMB extension