Conference Paper

Ultra-Fast CPU Performance Prediction: Extending the Monte Carlo Approach

New Mexico State Univ.
DOI: 10.1109/SBAC-PAD.2006.31 Conference: Computer Architecture and High Performance Computing, 2006. SBAC-PAD '06. 18TH International Symposium on
Source: IEEE Xplore


Performance evaluation of contemporary processors is becoming increasingly difficult due to the lack of proper frameworks. Traditionally, cycle-accurate simulators have been extensively used due to their inherent accuracy and flexibility. However, the effort involved in building them, their slow speed, and their limited ability to provide insight often imposes constraints on the extent of design exploration. In this paper, we refine our earlier Monte Carlo based CPI prediction model (Srinivasan et al., 2006) to include software assisted data-prefetching and an improved memory model. Software-based prefetching is becoming an increasingly important feature in modern processors but to the best of our knowledge, existing frameworks do not model it. Our model uses micro-architecture independent application characteristics to predict CPI with an average error of less than 10% when validated against the Itanium-2 processor. Besides accurate performance prediction, we illustrate the applications of the model to processor bottleneck analysis, workload characterization and design space exploration

1 Follower
13 Reads
  • Source
    • "We have both a single-and multi-core Niagara 2 model. All of these models are statistical and based on a Monte Carlo technique [6] [34] [35]. The Monte Carlo processor modeling technique is based on the equation, CP I = CP Ii + CP Is, where CP Ii is the ideal or intrinsic CPI based on the instruction issue width and CP Is is the CPI due to stalls (CPI is cycles per instruction ). "
    [Show abstract] [Hide abstract]
    ABSTRACT: As supercomputers grow, understanding their behavior and performance has become increasingly challenging. New hurdles in scalability, programmability, power consumption, reliability, cost, and cooling are emerging, along with new technologies such as 3D integration, GP-GPUs, silicon-photonics, and other "game changers". Currently, they HPC community lacks a unified toolset to evaluate these technologies and design for these challenges. To address this problem, a number of institutions have joined together to create the Structural Simulation Toolkit (SST), an open, modular, parallel, multi-criteria, multi-scale simulation framework. The SST includes a number of processor, memory, and network models. The SST has been used in a variety of network, memory, and application studies and aims to become the standard simulation framework for designing and procuring HPC systems.
    ACM SIGMETRICS Performance Evaluation Review 03/2011; 38(4):37-42. DOI:10.1145/1964218.1964225
  • Source
    • "To address these issues and to satisfy our own desire for performance models of contemporary processors, we developed a statistical modeling technique based on Monte Carlo methods that we believe can be applied to in-order and outof-order execution, multi-core processors. We introduced this method in [34] [33]; the method was presented in detail using the Niagara 2 model as an example in [10]. These previous models were all of in-order execution processors. "
    [Show abstract] [Hide abstract]
    ABSTRACT: Cycle-accurate simulation is the dominant methodology for processor design space analysis and performance prediction. However, with the prevalence of multi-core, multi-threaded architectures, this method has become highly impractical as the sole means for design due to its extreme slowdowns. We have developed a statistical technique for modeling multicore processors that is based on Monte Carlo methods. Using this method, processor models of contemporary architectures can be developed and applied to performance prediction, bottleneck detection, and limited design space analysis. To date, we have accurately modeled the IBM Cell, the Intel Itanium, and the Sun Niagara 1 and Niagara 2 processors [23, 22, 8]. In this paper, we present a work in progress which is applying this methodology to an out-of-order execution processor. We present the initial single-core model and results for the AMD Barcelona (Opteron) processor.
    ACM SIGMETRICS Performance Evaluation Review 03/2011; 38(4):75-80. DOI:10.1145/1964218.1964231
  • Source
    • "In this paper, we describe the modeling technique in detail, far beyond that presented before [1], [2], and we present statistical MCP models of both single-and multicore Niagara 2. This description and the subsequent presentation of the Niagara 2 processor model is meant to provide sufficient detail to enable the reader to develop his/her own MCP models if desired. This paper is primarily focused on the single-core model because building an accurate singlecore model is an essential first step to an accurate multicore model. "
    [Show abstract] [Hide abstract]
    ABSTRACT: With the complexity of contemporary single- and multi-core, multi-threaded processors comes a greater need for faster methods of performance analysis and design. It is no longer practical to use only cycle-accurate processor simulators for design space analysis of modern processors and systems. Therefore, we propose a statistical processor modeling method that is based on Monte Carlo techniques. In this paper, we present new details of the methodology and the recent extensions that we have made to it, including the capability to model multi-core processors. We detail the steps to develop a new model and then present statistical performance models of the Sun Niagara 2 processor micro-architecture that, together with a previously published Itanium 2 Monte Carlo model, demonstrates the validity of the technique and its new capabilities. We show that we can accurately predict single and multi-core performance within 7% of actual on average, and we can use the models to quickly pinpoint performance problems at various components.
    39th International Conference on Parallel Processing, ICPP 2010, San Diego, California, USA, 13-16 September 2010; 01/2010
Show more


13 Reads
Available from