Conference Paper

Requirements for Time-to-Digital Converters in the context of digital-PLL based Frequency Synthesis and GSM Modulation

Linz Center of Mechatronics GmbH
DOI: 10.1109/MWSYM.2006.249748 Conference: Microwave Symposium Digest, 2006. IEEE MTT-S International
Source: IEEE Xplore

ABSTRACT A key issue in proceeding the digitization of phase-locked loops (PLLs) is the realization of proper phase detectors in the digital domain. This paper presents simulative analysis of the properties and requirements for time-to-digital converters (TDCs) used for phase comparison in digitized fractional-N modulators with two-point modulation. Effects due to quantization of the TDC on frequency synthesis as well as GSM modulation quality are considered, defining the realization requirements for a transmitter

0 Bookmarks
 · 
44 Views
  • [Show abstract] [Hide abstract]
    ABSTRACT: State-of-the-art cellular transceivers are increasingly based on highly scaled CMOS technology nodes of 130 nm and beyond. In contrast to the ¿first generation¿ CMOS based transceivers, that were mainly a copy of there BiCMOS based counterparts in terms of architectures (e.g. direct-conversion receiver (DCR), direct modulation or PLL-based transmitters) and partitioning (e.g. analog I/Q interface), the ¿second generation¿ incorporated a by far more ¿digital¿ centric approach and took advantage of the technology capabilities. The ever increasing requirements towards multi-mode/multi-system capabilities favored the shift of functionality from the analog into the digital domain, due to the higher potential of digitally implemented features towards configurability. It can be anticipated that this trend towards digital centric architectures is further pushed by developments like cognitive radios (CR), dynamic spectrum access, interference management and advanced spectrum management.
    Radio-Frequency Integration Technology, 2009. RFIT 2009. IEEE International Symposium on; 01/2010
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper proposes and describes a new software and application programming interface view of an RF transceiver. It demonstrates benefits of using highly programmable digital control logic in an RF wireless system realized in a digital nanoscale CMOS process technology. It also describes a microprocessor architecture design in Digital RF Processor (DRP<sup>TM</sup>) and how it controls calibration and compensation for process, temperature and voltage variations of the analog and RF circuits to meet the required RF performance. A few calibration examples to reduce a DCO bias current and improve device reliability, as well as to optimize transmit modulation and receive performance, are given. The presented circuits and techniques have enabled successful implementation of a commercial single-chip GSM radio in 90 nm CMOS.
    IEEE Journal of Solid-State Circuits 01/2010; 45:276-288. · 3.06 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents a digital phase locked loop (DPLL) with two-step closed-locking technique. The two-step locking allows us to use a simple phase detector, which achieves wide phase detect range and has no complex circuits for glitch compensation. The DPLL has three digital controlled oscillators (DCO) for multi-mode/multi-band operation. The DPLL covers GSM quad-band, and several bands of WCDMA / LTE. The DPLL improves a close-in noise by 17 dB compared with the conventional count-assisted locking, which causes glitch error substantially. The phase error is less than 3.0 degrees in all bands for various conditions. The faraway phase noise is -165dBc/Hz at 20MHz, -161dBc/Hz at 190MHz, and -158dBc/Hz at 120MHz in each TX output, respectively.
    Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012