Conference Paper

Requirements for Time-to-Digital Converters in the context of digital-PLL based Frequency Synthesis and GSM Modulation

Linz Center of Mechatronics GmbH
DOI: 10.1109/MWSYM.2006.249748 Conference: Microwave Symposium Digest, 2006. IEEE MTT-S International
Source: IEEE Xplore


A key issue in proceeding the digitization of phase-locked loops (PLLs) is the realization of proper phase detectors in the digital domain. This paper presents simulative analysis of the properties and requirements for time-to-digital converters (TDCs) used for phase comparison in digitized fractional-N modulators with two-point modulation. Effects due to quantization of the TDC on frequency synthesis as well as GSM modulation quality are considered, defining the realization requirements for a transmitter

1 Follower
12 Reads
  • Article: Be flexible
    [Show abstract] [Hide abstract]
    ABSTRACT: The first section of this article gives an overview of standards that current multimode cellular phones must support. The paper then covers traditional analog architectures that were dominant in the SiGe-BiCMOS era and were also the basis for the first CMOS-based transceivers. Then the paper focuses on the extension to these architectures utilizing digital front-ends (DFEs) to enhance their flexibility and configurability. The final section gives an outlook to upcoming developments for CMOS nodes beyond 130 nm like all-digital phase locked loops (ADPLL) and sampling receivers.
    IEEE Microwave Magazine 05/2008; 9(2-9):83 - 95. DOI:10.1109/MMM.2008.915364 · 1.13 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: The idea of a ldquosoftware defined radiordquo (SDR) as proposed J. Mitola was quite a provoking vision beginning of the dasia90s. Even though the ideal SDR architecture mainly remained a subject of academic study so far it anticipated the need for an increased capability to reconfigure the RF-transceiver itself. This article gives a brief overview on the developments of cellular RF-transceivers during the last years in the light of the aforementioned need for reconfigurability. It specifically addresses the architectural changes that were on the one hand necessitated due to upcoming multi-system/multi-mode/multiband requirements and on the other hand favored by the step towards CMOS as mainstream technology even for the analog intensive RF-transceiver.
    Integrated Nonlinear Microwave and Millimetre-Wave Circuits, 2008. INMMIC 2008. Workshop on; 11/2008
  • [Show abstract] [Hide abstract]
    ABSTRACT: In digital phase-locked loop based fractional-N RF frequency synthesizers, the use of a Time-to-digital converter (TDC) as a quantized phase detector brings spurious emissions when synthesizing near-integer channel frequencies. The location of these fractional spurs is dependant on the resolution of the phase detector and the channel frequency being synthesized. In addition, spurs are also generated due to the non-uniform TDC quantization steps. This paper discusses a fast PLL simulation platform and a simulative analysis of the impact of SigmaDelta-noise cancellation on the fractional spurs.
Show more

Similar Publications