Requirements for Time-to-Digital Converters in the context of digital-PLL based Frequency Synthesis and GSM Modulation
Linz Center of Mechatronics GmbHDOI: 10.1109/MWSYM.2006.249748 Conference: Microwave Symposium Digest, 2006. IEEE MTT-S International
Source: IEEE Xplore
A key issue in proceeding the digitization of phase-locked loops (PLLs) is the realization of proper phase detectors in the digital domain. This paper presents simulative analysis of the properties and requirements for time-to-digital converters (TDCs) used for phase comparison in digitized fractional-N modulators with two-point modulation. Effects due to quantization of the TDC on frequency synthesis as well as GSM modulation quality are considered, defining the realization requirements for a transmitter
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ABSTRACT: In digital phase-locked loop based fractional-N RF frequency synthesizers, the use of a Time-to-digital converter (TDC) as a quantized phase detector brings spurious emissions when synthesizing near-integer channel frequencies. The location of these fractional spurs is dependant on the resolution of the phase detector and the channel frequency being synthesized. In addition, spurs are also generated due to the non-uniform TDC quantization steps. This paper discusses a fast PLL simulation platform and a simulative analysis of the impact of SigmaDelta-noise cancellation on the fractional spurs.
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