Conference Proceeding
A Passive UHF RFID Tag LSI with 36.6% Efficiency CMOS-Only Rectifier and Current-Mode Demodulator in 0.35/spl mu/m FeRAM Technology
Fujitsu Labs., Kawasaki
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
03/2006;
DOI:10.1109/ISSCC.2006.1696166
In proceeding of: Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Source: IEEE Xplore
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Citations (0)
- Cited In (3)
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Article: A Novel Passive Tag with Asymmetric Wireless Link for RFID and WSN Applications
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Article: Analysis and design of power efficient semi-passive RFID tag
[show abstract] [hide abstract]
ABSTRACT: The analysis and design of a semi-passive radio frequency identification (RFID) tag is presented. By studying the power transmission link of the backscatter RFID system and exploiting a power conversion efficiency model for a multi-stage AC–DC charge pump, the calculation method for semi-passive tag's read range is proposed. According to different read range limitation factors, an intuitive way to define the specifications of tag's power budget and backscatter modulation index is given. A test chip is implemented in SMIC 0.18 μm standard CMOS technology under the guidance of theoretical analysis. The main building blocks are the threshold compensated charge pump and low power wake-up circuit using the power triggering wake-up mode. The proposed semi-passive tag is fully compatible to EPC C1G2 standard. It has a compact chip size of 0.54 mm2, and is adaptable to batteries with a 1.2 to 2.4 V output voltage.Journal of Semiconductors 07/2010; 31(7):075013. -
Article: Design of a passive UHF RFID tag for the ISO18000-6C protocol
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ABSTRACT: This paper presents a new fully integrated wide-range UHF passive RFID tag chip design that is compatible with the ISO18000-6C protocol. In order to reduce the die area, an ultra-low power CMOS voltage regulator without resistors and an area-efficient amplitude shift keying demodulator with a novel adaptive average generator are both adopted. A low power clock generator is designed to guarantee the accuracy of the clock under ±4%. As the clock gating technology is employed to reduce the power consumption of the baseband processor, the total power consumption of the tag is about 14 μW with a sensitivity of −9.5 dBm. The detection distance can reach about 5 m under 4 W effective isotropic radiated power. The whole tag is fabricated in TSMC 0.18 μm CMOS technology and the chip size is 880 × 880 μm2.Journal of Semiconductors 05/2011; 32(5):055009.
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Keywords
15% power modulation
2.9-times higher 32b read-and-write throughput
lossless internal V<sub>th</sub> cancellation
mirror stack architecture
passive UHF RFID tag LSI
power efficiency
