Conference Proceeding

A 1/4 rate linear phase detector for PLL-based CDR circuits

Sharif Univ. of Technol.
06/2006; DOI:10.1109/ISCAS.2006.1693326 pp.4 pp. - 3284 In proceeding of: Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Source: IEEE Xplore

ABSTRACT In this paper, a new frac14 rate clock linear phase detector (PD) structure for PLL-based clock and data recovery (CDR) circuits is suggested. The proposed topology offers a more suitable PD for high speed applications compared to the conventional topologies. The effect of duty cycle variation on the operation of CDR has been also studied. Designed in a 0.18mum CMOS technology, the proposed PD consumes 16mA from a 1.8V voltage supply

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Keywords

1.8V voltage supply
 
conventional topologies
 
duty cycle variation
 
new frac14 rate clock linear phase detector
 
PD
 
proposed PD consumes 16mA
 
proposed topology
 
speed applications
 
suitable PD