A sensor system on chip for wireless microsystems
ABSTRACT Recent years have seen the rapid development of microsensor technology, system on chip design, wireless technology and ubiquitous computing. When assembled into a complex microsystem the technologies become powerful tools in medical diagnostics, environmental monitoring and personal connectivity. In this paper we describe the demonstration of a silicon chip that has all the attributes required of a microsystem for use in these applications. The design methodology we have employed is a variant of the system on chip approach whereby many intellectual property blocks are integrated at a high level in the design flow. Our intellectual property blocks include the analogue sensor instrumentation for temperature and pH, a data multiplexing and conversion module, a digital platform based around an 8-bit microcontroller, data encoding for spread-spectrum wireless transmission and a RF section requiring very few off-chip components. The chip has been fully evaluated and tested by connection to external sensors. Each block has well defined interfaces so that they can be easily reused in future designs targeted to different applications
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A SENSOR SYSTEM ON CHIP FOR WIRELESS MICROSYSTEMS
L. Wang1, N. Aydin2, A. Astaras3, M. Ahmadian2, P. A. Hammond1, T. B. Tang2, E. Johannessen1, T. Arslan2,
S. P. Beaumont3, B. W. Flynn2, A. F. Murray2, J. M. Cooper1, D. R. S. Cumming1
1 Department of Electronics and Electrical Engineering, University of Glasgow, Glasgow, U.K.
2 School of Engineering and Electronics, University of Edinburgh, Edinburgh, U.K.
3 The Institute for System Level Integration, The Alba Campus, Livingston, U.K.
Recent years have seen the rapid development of
microsensor technology, system on chip design, wireless
technology and ubiquitous computing. When assembled
into a complex microsystem the technologies become
powerful tools in medical diagnostics, environmental
monitoring and personal connectivity. In this paper we
describe the demonstration of a silicon chip that has all
the attributes required of a microsystem for use in these
applications. The design methodology we have employed
is a variant of the system on chip approach whereby
many intellectual property blocks are integrated at a high
level in the design flow. Our intellectual property blocks
include the analogue sensor instrumentation for
temperature and pH, a data multiplexing and conversion
module, a digital platform based around an 8-bit micro-
controller, data encoding for spread-spectrum wireless
transmission and a RF section requiring very few off-chip
components. The chip has been fully evaluated and
tested by connection to external sensors. Each block has
well defined interfaces so that they can be easily reused
in future designs targeted to different applications.
Keywords: System-on-chip, sensors, microsystems
The ability to integrate complete sensor systems into a
very small form-factor is of growing importance as
applications such as ubiquitous computing, micro-total-
analytical-systems (µTAS) and personal biomedical
monitoring become more widespread . Examples are
the development of Smartdust that uses micro-electro-
mechanical systems (MEMS) technology to explore the
extremes of miniaturization, micro-robotics for gastro-
intestinal investigation and sophisticated wireless
networks using relatively large (hand-held) devices [2, 3].
In this Paper we describe the development of an
integrated circuit system on chip (SOC) that aims to
combine many of the functions of a sensor-based
microsystem on to a single substrate. Our design is
specified for a biosensor system with up to eight pH and
temperature data channels communicating via an encoded
wireless interface to a remote data acquisition (DAQ)
device. The system comprises analogue instrumentation,
data conversion circuits, a micro-controller, a data
encoder and a frequency shift keying (FSK) RF
transmitter. Many of the system blocks are from pre-
existing libraries, or have been written and imported in an
intellectual property (IP) block form, thus the design
represents the first steps towards a sensor system-on-chip.
SENSOR SYSTEM ON CHIP
Figure 1 shows the schematic of the SOC. The design
flow used to create the SOC was relatively
straightforward. Cadence tools were used for
analogue/digital simulations and back-end design tasks
and Synopsys tools were used for digital synthesis of
VHDL behavioural and
descriptions. Transistor-level or gate-level simulations
were used to verify that all functional blocks worked as
desired before chip assembly and implementation. The
architecture and the software routines, was verified by
writing to a XILINX SPARTANII-FPGA followed by
board-level testing to ensure proper functionality before
committing to silicon.
register transfer level
including the hardware
The system operates with pH (acidity/alkalinity) and
temperature sensors . The pH sensor is an ion
sensitive field effect transistor (ISFET) and has a
Nernstian response with respect to pH. Unfortunately the
device also has a response to temperature change that
must be calibrated for. As a consequence the temperature
sensor is not only required to provide a temperature
reading per se, but is also required to enable calibration
of the pH sensor.
The temperature sensor is a forward biased pn junction
with a junction area of 0.6 mm2. The detector circuit is a
conventional structure that connects the diode in feedback
across an operational amplifier with a constant bias
current. The operational amplifier is a MOSFET based
device taken from the foundry library prepared by Austria
Mikro Systeme (AMS). An on chip bias resistor sets the
constant current to be approximately 15 µA. The signal
is then buffered and amplified by a factor of 10 before
being presented to the input of an analogue multiplexer.
The reverse bias saturation current of the diode is 30 pA
and the ideality factor is approximately 2 therefore the
device sensitivity (including gain) is ≈ 22 mV/oC, but
does vary from device to device due to tolerances.
ISCAS 20060-7803-9390-2/06/$20.00 ©2006 IEEE
pH circuitpH circuit
T circuitT circuit
: digital data: digital data
: analogue data: analogue data
: control signal
: clock signal: clock signal
: control signal
Figure 1 A schematic diagram of the sensor-system on chip architecture.
The external pH-ISFET sensor forms the load of a 33 µA
cascode current sink as shown in Fig. 2. The ISFET has
an intrinsic gate referred sensitivity of 43 mV/pH point.
The output transistors of the cascode circuit form an
active load to the ISFET that is configured as a source-
follower, thus the voltage swing at the source of the
ISFET responds at 43 mV/pH point.
Figure 2 A schematic of the pH sensor circuit.
The analogue to digital interface circuitry comprises
seven 2-input multiplexers and a 10-bit successive
approximation analogue-to-digital converter (ADC) taken
from the AMS library. The multiplexers allow eight
sensor channels to be presented to the single ADC for 0.3
ms each hence 2.4 ms is required to sample all eight
channels. The system sample rate is 0.5 S/s, by which we
mean all 8 channels are sampled once in every 2 s.
In order to minimise the off-chip component count, hence
the overall packaged system size an on-chip RC
relaxation oscillator (the timer) was used. The timing
precision of the oscillator is poor due to the fabrication
tolerance of on-chip resistors and capacitors, but this
imprecision is not important in the context of the
complete data acquisition system . The nominal
frequency of the RC oscillator is set to be 8 MHz, but it
measured only 7.1±0.1 MHz on a batch of 10 fabricated
chips. The timer circuit also contains a digital divider
designed to generate different clocks for the ADC (250
kHz), the micro-controller (250 kHz) and the data
encoder (32 kHz). The clock rates for these blocks were
224 kHz, 224 kHz and 29 kHz respectively because of the
shift of the nominal oscillator frequency. In addition to
generating the system clocks the timer also generates a
positive pulse (lasting 5 microseconds) every 2 s to
“awake” the micro-controller.
The micro-controller was designed by us to have the
same instruction set, excluding the multiply (MUL) and
WAIT instructions, as a Motorola® 6805 CPU. The
hardware architecture and the software routines of the
micro-controller were co-designed to achieve better
system performance. The micro-controller was designed
to be fully static and was implemented with a further of
512 bytes ROM, 32 bytes RAM (24 bytes for buffers and
8 bytes for stack), 3 bi-directional 8-bit I/O ports and a
16-bit capture/compare timer system. The software
routines, embedded into the 512-byte ROM, were used
for scheduling different tasks such as channel cycling and
sampling and automatically goes into a sleep mode when
all tasks are finished. However, every 2 s, the
aforementioned positive pulse invokes a rising-level
sensitive interrupt of the micro-controller, and forces the
micro-controller go back to an active mode. In the
present design 25% of the total operation time is spent in
the sleep mode thus a significant amount of power
consumption is saved. This external interrupt design also
enables dynamic reconfiguration of the system sample
rate . For example, by simply setting different time
intervals between the positive pulses, the micro-controller
can be invoked at varying time intervals in order to suit
different applications and data needs. All output data is
coded as a serial bit stream packet by the micro-
A programmable direct-sequence spread spectrum (DS-
SS) transmitter was integrated into the SOC with very
few off-chip components in order to provide more than
one channel and coding gain. A block diagram of the
transmitter is shown in Fig. 3. The core of the DS-SS
transmitter is the pseudo-random noise (PN) code
generator . The PN code length was programmable to
provide the appropriate amount of data spreading for a
Figure 3 The block diagram of the DS-SS transmitter.
Serial bit stream data to be transmitted is coded by either
the PN code if the bit is logic 0 or a 180 degree phase
shifted version of the PN code if the bit is logic 1. For
these PN code lengths of 256, 128, 64, and 32 bits, it
takes approximately 34 µs, 68 µs, 136 µs and 273 µs,
respectively, to present one code. The minimum data rate
from the encoder was therefore approximately 3.67 Kb/s.
The encoder’s output can be directly fed into a
commercially available small transmitter (TX) module,
however, where further miniaturisation (e.g. implantable
applications) is important the integrated RF section can
be activated. A relatively low carrier frequency of 40
MHz was selected for the on-chip RF section because, in
applications such as the laboratory-in-a-pill it is expected
that low frequency signals will be less strongly absorbed
. The carrier frequency signal was generated directly
using a Colpitts oscillator with an external crystal. A
variable capacitor in series with the crystal was used to
generate FSK modulation. The RF signal can be taken
off-chip to an external antenna, or alternatively, an on-
chip spiral inductor (approximately 800µm x 300µm)
incorporated on the SOC can be used. The radiated
signal from the inductor was weak, but it was detectable
at a range of 0.2 m in air using a Winradio® receiver
(with a conventional whip antenna) at a data rate of up to
5 Kb/s. It must be noted that the inductor was less
efficient and more direction sensitive than external
antennas, however, it demonstrated the possibilities of
integrated on-silicon antennas that could be used for
short-range body-centric wireless sensor applications .
The output signal from the Winradio receiver was
acquired by a DAQ device (National Instruments
DaqPad-6020E). Since the DAQ terminal uses a
correlator implemented on a PC in software, the
synchronization requirement between the SOC and the
terminal was significantly reduced. The correlator will
yield a positive peak at 00 phase, and a negative peak at
1800 phase. Data can be simply recovered by thresholding
the correlator output. Figure 4 shows an experimentally
obtained decoded signal after normalized autocorrelation
(with the on-chip RF section activated). It shows that
different bit values (1 or 0) were correctly recognized
despite the noisy background introduced by the wireless
Figure 4 An experimentally obtained trace of ‘0’s and ‘1’s with
value (after normalized correlation) –1 and 1 respectively.
The sensor interfaces, the system platform and the
wireless interface were implemented on a 4.1 mm x 4.1
mm mixed signal SOC prototype, including a second ring
of 100 µm x 200 µm pads, added to ease manual bonding
in laboratory-in-a-pill prototypes. Without this additional
pad-ring the chip size would be 3.5 mm x 3.5 mm. The
chip was fabricated using a 3-metal, 2-poly 0.6µm CMOS
process provided by the AMS, via the European
Europractice initiative. Finished chips were returned
both as unpackaged die (Fig. 5) and in 84-pin J-Leaded
Ceramic Chip Carrier (JLCC) packages for test purposes.
The SOC is core-limited; its core has implemented 42K
transistors and occupied 6.3 mm2 of silicon area. Of the
84 pads, 24 are power pads and 60 are I/O pads, more
than 75 % of which are used for preliminary chip tests.
Figure 5 A micrograph of the fabricated system on chip
showing the system blocks.
The SOC was designed to minimize the propagation of
noise from the noisy oscillators to the noise-sensitive
sensor interface circuitry, and particularly to the
operational amplifier input nodes . These circuits were
physically isolated on the silicon die, their power supplies
were separated inside the chip and additional substrate
noise barriers (guard rings) were placed around them.
Moreover, the core and pad ring power supplies were also
separated inside the chip, and the pad ring was split into
analogue, digital and RF sections to inhibit noise from
propagating through power lines. Finally, approximately
20pF of power supply decoupling capacitance was
Testing of the SOC revealed that the biggest contributor
of noise that reaches the analogue amplifier inputs is the
crystal-controlled oscillator. It generates 15 mVrms and
25 mVrms of noise at 20MHz and 40MHz respectively,
as measured at the operational amplifier input nodes. The
on-chip RC oscillator operating at 7.1 MHz generates 13
mVrms of noise as measured at the operational amplifier
input nodes and produces significantly lower peak-to-
peak noise in the same measurement configurations. In
general, the noise measured on an output pin from the
analogue circuit (before the ADC), when powered by two
batteries, equals to approximate 15 mVrms.
The packaged SOC was plugged into a printed circuit
board and powered up by two SR44 silver oxide cells
attached using short leads. The battery voltage decreases
with use and the average power consumption of the SOC
measures 13.5 mW at 3.0 V. The largest power
consumptions are from the sensor interfaces (6.6 mW at
3.0 V) and RF sections (5.1 mW at 3.0 V). The power
consumption for the digital blocks (1.8 mW at 3.0 V) is
presented for the aforementioned operating frequencies
used in each blocks. With the on-chip RF section
activated, the maximum measured power consumption
for new batteries was 18 mW, decaying to 8 mW for
batteries approaching the end of their lifetime. Overall
lifetimes in the range of 20 – 25 hours were achieved.
A temperature sensor and a pH sensor were connected to
the sensor interfaces. The output signal from the system
platform was fed into the encoder, but not using the on-
chip RF section. Instead the encoder output signal was
fed into an external TX module via pad-ring connections.
The Winradio receiver with a conventional whip antenna,
the DAQ device and a laptop computer with appropriate
data processing software were configured for use as the
DAQ and data presentation terminal. The encoder was
assigned the lowest data transmission rate 3.67 Kb/s, and
the DAQ over-sampling rate was set to be 10 KS/s in
order to correctly sample the signal. For calibration
purposes, the sensors were first dipped into specified pH
buffer solutions at known temperatures in the range 30 to
90 °C. Once calibrated, approximately 25 minutes of
data was acquired for each experimental run. Readings
from standard temperature and pH meters were
simultaneously recorded for comparison. From this study
we were able to confirm that the sensor interfaces, the
system platform and the data encoder were working
Finally, the SOC, comprising the sensor interface, the
system platform and the complete wireless interface was
tested. The output of the encoder was fed into the on-
chip RF section with an external crystal to tune the
transmitter. No external TX module was connected and
the Winradio receiver was again used for continuity. The
data transmission rate of the encoder was set to be same
as before. Results in Fig. 6 indicate the complete SOC
works as intended. The results are comparable with those
obtained using the external TX module.
In this paper we have presented a biosensor system
architecture incorporating a fully specified and functional
system-on-chip to acquire, process and communicate data
wirelessly. We believe that the concept we present here
can be greatly developed to introduce sensor-SOC into a
diverse range of applications.
Figure 6 Experimental results of (a) one temperature channel
and (b) one pH channel. The two channels can be operated
simultaneously in real time.
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