A Power-Aware Technique for Functional Units in High-Performance Processors
ABSTRACT This paper presents a hardware technique to reduce the static and dynamic power consumption in functional units of a 64-bit superscalar processor. Our approach is based on substituting some of the 64-bit power-hungry adders by others with 32-bit lower power-consumption adders, and modifying the protocol in order to issue as much instructions as possible to those low power-consumption units incurring a negligible performance penalty. Our technique saves between 14.7% and a 50% of the power-consumption in the adders which is between 6.1% and a 20% of power-consumption in the execution units. This reduction is important because it can avoid the creation of a hot spot on the functional units
SourceAvailable from: psu.edu
Conference Paper: Power minimization of functional units by partially guarded computation[Show abstract] [Hide abstract]
ABSTRACT: This paper deals with power minimization problem for data-dominated applications based on a novel concept called partially guarded computation. We divide a functional unit into two parts: MSP (Most Significant Part) and LSP (Least Significant Part) and allow the functional unit to perform only the LSP computation if the range of output data can be covered by LSP. We dynamically disable MSP computation to remove unnecessary transitions thereby reducing power consumption. We also propose a systematic approach for determining optimal location of the boundary between the two parts during high-level synthesis. Experimental results show about 10∼44% power reduction with about 30∼36% area overhead and less than 3% delay overhead in functional units.Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on; 02/2000
[Show abstract] [Hide abstract]
ABSTRACT: Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high accuracy by calculating power estimates for designs only after layout or floorplanning are complete In addition to being available only late in the design process, such tools are often quite slow, which compounds the difficulty of running them for a large space of design possibilities.
[Show abstract] [Hide abstract]
ABSTRACT: Reduction in leakage power has become an important concern in lowvoltage, lowpower and high performance applications. In this paper, we use dual threshold technique to reduce leakage power by assigning high threshold voltage to some transistors in non-critical paths, and using lowthreshold transistors in critical paths. In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high threshold voltage. A general standby leakage current model which has been veri#ed by HSPICE is used to estimate standby leakage power. Results show that dual threshold technique is good for power reduction during both standby and active modes. The standby leakage power savings for some ISCAS benchmarks can be more than 50#. 1 Introduction With the growing use of portable and wireless electronic systems, reduction in power consumption has become more and more importantintoday's VLSI circuit and system designs #1#, ...