Conference Paper

Design of an Embedded Fingerprint Matcher System

Electron., Electr. & Autom. Eng. Dept., Univ. Rovira i Virgili, Tarragona
DOI: 10.1109/ISCE.2006.1689467 Conference: Consumer Electronics, 2006. ISCE '06. 2006 IEEE Tenth International Symposium on
Source: IEEE Xplore

ABSTRACT The current technological age is demanding reliable and cost-effective personal authentication systems for a wide range of daily use applications such as access control, electronic commerce, ID verification... where security and confidentiality performance of the information is needed. Biometrics-based authentication techniques (e.g. face, iris, fingerprint recognition...) in conjunction with embedded systems technologies bring a challenging solution to this need. This paper describes the hardware-software co-design of a computational platform responsible for matching two fingerprint minutiae sets. A novel system concept is suggested by making use of reconfigurable architectures

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    ABSTRACT: The embedded devices in biometrics have gained increasing attention due to the demand for reliable and cost-effective personal identification systems. However, the current available embedded devices are not suitable for the real-time implementation of a biometric application system because of the limited computational resource and memory space. In this paper, we describe the design of embedded biometric systems that identify person by using face-fingerprint or iris-fingerprint multimodal biometrics technology. To implement real-time system, the biometric algorithms are efficiently enhanced for fixed-point representation and optimized for memory and computational capacity. In addition, the most time consuming components of each biometric algorithm are implemented in a Field Programmable Gate Arrays (FPGA).
    Signal-Image Technologies and Internet-Based System, 2007. SITIS '07. Third International IEEE Conference on; 01/2008
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    ABSTRACT: Nowadays the development of automatic biometrics-based personal recognition systems is a reality in the current technological age. Not only those applications demanding stringent security levels but also many daily use consumer applications request the existence of high performance computational platforms in charge of recognizing the identity of an individual based on the analysis of his/her physiological or behavioural characteristics. The state of the art points out two main open problems in the implementation of such automatic applications: on the one hand, the needed improvement of the reliability level of the existing recognition systems in terms of accuracy, security and real-time performances; on the other hand, the cost reduction of those physical platforms in charge of the processing.This work addresses those limitations of current systems and aims at finding the proper system architecture to develop this kind of high-performance applications at low cost. Because of that, those existing solutions based on expensive multiprocessor systems like HPC (High Performance Computer), GPU (Graphics Processing Unit), or PC (Personal Computer) platforms need to be discarded, and instead of them embedded system solutions based on programmable logic devices are suggested in this work. The programmability performances of FPGA (Field Programmable Gate Array) devices together with the inherent parallelism of hardware design provide the needed flexibility to develop made-to-measure coprocessors in charge of accelerating those time-critical computational tasks. To address the cost of the system, dynamically reconfigurable FPGAs are suggested in this work. The scheduling of the recognition application into a series of mutually exclusive tasks, and the reutilization of those functional resources available in the FPGA by multiplexing different coprocessors in the same area along the application execution time allows reducing the size of the device and therefore its cost at the expense of the reconfiguration overhead.The hardware–software co-design of an AFAS (automatic fingerprint-based authentication system) under two different run-time reconfigurable platforms is presented as the proof of concept of the suggested architecture. The outstanding results achieved in this work pave the way for the implementation of biometric applications by means of run-time reconfigurable FPGAs.
    Future Generation Computer Systems 01/2012; 28:268-286. · 2.64 Impact Factor

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