Design of an Embedded Fingerprint Matcher System
ABSTRACT The current technological age is demanding reliable and cost-effective personal authentication systems for a wide range of daily use applications such as access control, electronic commerce, ID verification... where security and confidentiality performance of the information is needed. Biometrics-based authentication techniques (e.g. face, iris, fingerprint recognition...) in conjunction with embedded systems technologies bring a challenging solution to this need. This paper describes the hardware-software co-design of a computational platform responsible for matching two fingerprint minutiae sets. A novel system concept is suggested by making use of reconfigurable architectures
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Conference Paper: Design of Embedded Multimodal Biometric Systems[Show abstract] [Hide abstract]
ABSTRACT: The embedded devices in biometrics have gained increasing attention due to the demand for reliable and cost-effective personal identification systems. However, the current available embedded devices are not suitable for the real-time implementation of a biometric application system because of the limited computational resource and memory space. In this paper, we describe the design of embedded biometric systems that identify person by using face-fingerprint or iris-fingerprint multimodal biometrics technology. To implement real-time system, the biometric algorithms are efficiently enhanced for fixed-point representation and optimized for memory and computational capacity. In addition, the most time consuming components of each biometric algorithm are implemented in a Field Programmable Gate Arrays (FPGA).Signal-Image Technologies and Internet-Based System, 2007. SITIS '07. Third International IEEE Conference on; 01/2008
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ABSTRACT: Nowadays the development of automatic biometrics-based personal recognition systems is a reality in the current technological age. Not only those applications demanding stringent security levels but also many daily use consumer applications request the existence of high performance computational platforms in charge of recognizing the identity of an individual based on the analysis of his/her physiological or behavioural characteristics. The state of the art points out two main open problems in the implementation of such automatic applications: on the one hand, the needed improvement of the reliability level of the existing recognition systems in terms of accuracy, security and real-time performances; on the other hand, the cost reduction of those physical platforms in charge of the processing.This work addresses those limitations of current systems and aims at finding the proper system architecture to develop this kind of high-performance applications at low cost. Because of that, those existing solutions based on expensive multiprocessor systems like HPC (High Performance Computer), GPU (Graphics Processing Unit), or PC (Personal Computer) platforms need to be discarded, and instead of them embedded system solutions based on programmable logic devices are suggested in this work. The programmability performances of FPGA (Field Programmable Gate Array) devices together with the inherent parallelism of hardware design provide the needed flexibility to develop made-to-measure coprocessors in charge of accelerating those time-critical computational tasks. To address the cost of the system, dynamically reconfigurable FPGAs are suggested in this work. The scheduling of the recognition application into a series of mutually exclusive tasks, and the reutilization of those functional resources available in the FPGA by multiplexing different coprocessors in the same area along the application execution time allows reducing the size of the device and therefore its cost at the expense of the reconfiguration overhead.The hardware–software co-design of an AFAS (automatic fingerprint-based authentication system) under two different run-time reconfigurable platforms is presented as the proof of concept of the suggested architecture. The outstanding results achieved in this work pave the way for the implementation of biometric applications by means of run-time reconfigurable FPGAs.Future Generation Comp. Syst. 01/2012; 28:268-286.
1-4244-0216-6/06/$20.00 ©2006 IEEE
Design of an Embedded Fingerprint Matcher System
Mariano Fons, Francisco Fons, Enrique Cantó
Abstract — The current technological age is demanding
reliable and cost-effective personal authentication systems
for a wide range of daily use applications such as access
control, electronic commerce, ID verification... where
security and confidentiality performance of the information
is needed. Biometrics-based authentication techniques (e.g.
face, iris, fingerprint recognition...) in conjunction with
embedded systems technologies bring a challenging
solution to this need. This paper describes the hardware-
software co-design of a computational platform responsible
for matching two fingerprint minutiae sets. A novel system
concept is suggested by making use of reconfigurable
Index Terms — Biometrics, Fingerprint minutiae-based
matching, System-on-chip technology, Hardware-software co-
design, Reconfigurable hardware, Embedded system.
Among all physiological (e.g. hand geometry, fingerprint,
face, iris...) and behavioural (e.g. handwriting, gait, voice
print...) human characteristics, fingerprint is the most deeply
used technique for personal recognition. Authors focus their
work on fingerprint biometrics and hardware-software co-
design technology in order to define a new system
architecture conception for AFAS (Automatic Fingerprint
Authentication Systems) . The goal of AFAS is to
efficiently verify the identity of an individual by means of
his/her genuine fingerprint characteristics. Two are the
stages involved in the recognition process:
During the first stage, called enrolment, the system
measures the biometric characteristics of the user. From this
measurement, it generates a template that is stored, together
with any other relevant information of the user, in a secure
memory or database. After the enrolment phase, the user
becomes available in the system so he can be properly
identified in the second stage of the recognition process: the
During the authentication stage, the user’s biometric
characteristic is measured again and compared against the
previously stored template. If they are similar enough, it is
assumed that the person previously enrolled is now present.
However, if both biometrics are different, it is deduced that
the current user is an impostor, and he is not who he claims
to be. As a result of the biometric authentication process the
1 M. Fons, F. Fons, and E. Cantó are with the Electronic, Electrical and
Automation Engineering Department, University Rovira i Virgili (URV),
Tarragona, 43007 SPAIN (e-mail: email@example.com,
system either accepts or rejects the user, improving thus the
robustness and security of the overall application against
The main tasks involved in the personal recognition
- Fingerprint image acquisition. Although in the past the
fingerprint acquisition was performed manually by means of
ink and paper, nowadays electronic fingerprint sensors and
capture methods have been developed in order to automate
the acquisition process. As a result of this first step, a digital
greyscale image of the user’s fingerprint is obtained.
- Image processing. In order to improve the quality of the
input print, several pre-processing stages are applied to the
original image to eliminate those noisy regions and to adapt
the image to the following processing steps. From these
tasks, a quality filter can be applied to the input images,
rejecting thus those low quality fingerprint impressions.
- Feature extraction. In this stage several complex
algorithms such as gradient map computation, image
segmentation, brightness and contrast enhancement,
orientation field calculation, bitmap binarization and ridge
thinning can be applied to the image prior to extracting
those distinctive characteristics of the fingerprint. Normally,
the ridge discontinuities of the fingerprint, called minutiae
and mainly based on the ridge endings and the ridge
bifurcations of the fingertip, are the features extracted in this
- Feature matching. It consists of deducing the
correspondence among those features obtained from two
different finger impressions. The matching process will give
as result the confidence to determine if both fingerprints
come (or not) from the same finger (user).
Although the accuracy of the recognition system does
depend on the reliability of every stage involved, fingerprint
matching has special influence on the final system
performance. Following this direction, the current article is
focused on the fingerprint matching stage, without taking
care about previous processing stages.
As it can be deduced from the complexity of the different
tasks involved in a personal recognition process (Fig. 1 and
Fig. 2), the implementation of an AFAS demands a high
computational power. Nowadays, AFAS are mainly based
on software solutions , : conventional computer
platforms based on powerful microprocessors running
complex tasks at high speed. However, with the advances
recently made in VLSI (Very Large Scale Integrated)
technology, the hardware-software co-design techniques
together with dynamically reconfigurable architectures have
become a challenging alternative.
Fig. 1. Tasks involved in the enrolment process: fingerprint image acquisition, image processing, feature extraction and feature storage (in a secure
database or a smart card) for the template fingerprint.
Implementing those complex computational tasks on
hardware (ASIC, FPGA) while keeping those less
expensive tasks on software (MCU) yield significant
improvements in execution times. Owing to the fact that the
current technological age is demanding reliable and cost-
effective personal authentication systems for a wide range
of daily use applications, a novel AFAS architecture is
suggested in this work. A special attention is done to the
definition of a cost-effective-oriented system, able to
convert personal security in a pervasive service, accessible
to everybody, anywhere and anytime, in the same way as
mobile phone technology does perform today within the
current communications age.
The rest of the paper is organized as follows. In section
2, the proposed system architecture is presented. The
fingerprint matching algorithm selected to be implemented
into the system is detailed in section 3. The hardware-
software partitioning of the application is covered in section
4. The experimental results are shown in section 5. Finally,
the conclusions and the future work are summarized in
II. SYSTEM ARCHITECTURE
The conventional AFAS architecture is based on personal
computer platforms and several functional blocks:
CPU, as heart of the system;
DSP and floating-point coprocessors, specially
designed to accelerate those complex mathematical
ROM memory, where to allocate the operating
Non-volatile EEPROM or FLASH memory, to store
specific application data (e.g. user’s fingerprint
templates) and/or program code;
RAM memory, acting as processor’s working
and I/O interface, used as communication channel to
transfer/receive data to/from outside.
However, a novel system architecture is presented in this
work. The development of a small computational platform
is intended by fitting those resources specifically required
by the application. A novel topology is suggested by taking
profit of the advantages that application specific hardware
implementation offers in comparison with a purely software
For this purpose, current work makes use of the
advantages of Field Programmable Gate Arrays technology.
FPGAs are configurable VLSI devices where it is possible
to synthesize application specific logic functions by
hardware, and exploit the parallelism and pipelining
features available in these devices. The current FPGA
technology also includes the notion of reconfigurability
performance, based on the capability of modifying the
hardware content throughout the application execution time.
Fig. 2. Tasks involved in the authentication process: fingerprint image acquisition, image processing and feature extraction stages for the query
fingerprint; fingerprint feature reading for the template fingerprint;
and fingerprint matching of both, template and
Image ProcessingImage Acquisition
Image ProcessingImage Acquisition
Feature ReadingTemplate Feature
The suggested platform is mainly based on a
microprocessor, its memory block and a dynamically
reconfigurable FPGA, as shown in Fig. 3.
Fig. 3. Main physical blocks in the proposed fingerprint-based
There already exist some works in literature that make
use of FPGAs or embedded platforms to implement matcher
or complete authenticator systems , . However,
innovative research arises on automatic fingerprint
authenticator systems making use of reconfigurable FPGAs.
The flexibility performance reached by the reconfigurable
FPGA allows using it as a multipurpose device where it is
possible to implement several computational functions
multiplexed in time. Specific mathematical, digital-image or
biometric coprocessors can be dynamically synthesized on
the FPGA to speed up the personal authentication process.
The reconfigurable hardware gives additional flexibility
to the system, increasing consistently the workload
capability of the platform in comparison with a general-
purpose personal computer. Application-specific functions
are downloaded into the FPGA as they are needed along the
execution time, thus reducing drastically the area needs for
the device in comparison with the static implementation of
all functional modules in a non-reconfigurable FPGA.
In this new topology, the FPGA is used to implement
specific coprocessors multiplexed in time, whereas the
microprocessor is responsible for managing the biometric
authentication process, as well as taking care of the FPGA
Fig. 4. Main functional blocks in the proposed fingerprint-based
Although the main goal of this work is to check the
feasibility of this new architecture proposal, special
attention has to be taken to the reconfiguration overhead.
The reconfiguration of the FPGA must not overload the
application execution time. The timing constraints imposed
by the application will set the maximum overload
admissible for reconfigurability tasks. The microprocessor
becomes the master scheduler, and controls and monitors all
activities that take place during the recognition process.
The complete block diagram suggested in this paper is
depicted on Fig. 4. An electronic fingerprint sensor is also
integrated into the system in order to allow the automatic
fingerprint acquisition stage.
III. FINGERPRINT MATCHING ALGORITHM
The fingerprint matching algorithm is responsible for
generating a similarity score for the input and template
prints. After similarity analysis, the comparison of the
resultant match score with a certain threshold will state
whether both original fingerprints are generated (or not)
from the same finger.
Many methods for matching two fingerprints have been
presented in literature . Among them, minutia-based
(fingerprint ridge discontinuities: ridge endings and ridge
bifurcations) is the most widely used technique due to its
good performance with less computational costs (processing
time and memory needs) than other techniques. Matching
two fingerprints in minutia-based representations becomes a
point pattern-matching problem, and it consists of finding
the alignment and correspondences between pairs of
minutiae points in both sets.
The proposed algorithm is abstracted from  and .
They use both local and global structures of minutiae to
perform fingerprint alignment and matching. Some
modifications have been introduced to the original
algorithms in order to improve the matching performance
results. The matching process is split in several sequential
steps, as described in the following sections.
A. Minutia Description: Local Analysis
In order to determine the similarity of fingerprints, first
the local structure of every minutia point in both minutiae
sets is obtained. The local structure describes the spatial
characteristics of a minutia
neighbourhood into account. This local descriptor is a
rotation and translation invariant feature, inherent to a
The relative Euclidean distances d (1) and angles φ (3)
between the specific minutia and its nearest N minutiae
neighbours, as well as the relative ridge directions γ (4) are
used in order to clearly define the local neighbourhood of a
minutia. Every minutia is then well defined by N relative
triplets (d,φ,γ), thus a minutiae set composed by W minutia
points is then characterized by W x N triplets (d,φ,γ).
taking its minutiae
CPUI / O
FEATURE MATCHING UNIT
Fig. 5. Fingerprint minutia descriptor (d, φ, γ), where m0 (x0, y0, β0) is a
ridge ending and m1 (x1, y1, β1) is a ridge bifurcation.
Normally, a fingerprint impression contains W=30-50
minutia points, and authors have selected N=8 neighbours
as neighbourhood criterion.
B. Minutia Comparison: Similarity Matrix
Once template and input minutiae are properly defined,
next step consists of finding the correspondence between
minutia pairs in both sets. Given a template minutiae with T
minutia points and an input minutiae with I minutia points,
a T x I similarity matrix is built in order to analyze the
similarity score between any possible minutia pair
combination. To cope with the inevitable non-linear
distortions originated during the fingerprint acquisition
stage, when mapping a 3-dimensional and elastic fingertip
onto a 2-dimensional sensor plane, small local deformations
are allowed when determining the similarity level between
C. Central Feature Selection
The similarity scoring of local structures permits to
identify the best-matched minutia pair and take it as
reference to align both global structures (fingerprints).
D. Minutiae Description: Global Analysis
In the same way as a minutia is defined by its local
structure, a minutiae set is defined by its global structure.
The global structure describes the spatial characteristics of
the minutiae from a reference minutia point (central
feature). Given a minutiae set composed by W minutia
points, and once determined its central feature, the minutiae
is then characterized by (W-1) triplets (d,φ,γ) relative to the
central feature point.
E. Decision Making: Match Result
Once the global definition of both minutiae sets is done,
the global correspondence analysis guarantees that one
minutia of the template minutiae can be paired at most with
one minutia of the input minutiae. A set of global minutia
pairs is obtained, allowing certain elastic tolerances in them.
From the location of the corresponding minutia pairs it is
possible to select the regions of interest on both
fingerprints. These regions of interest can be interpreted as
the overlapped areas between both prints, and from them a
similarity score can be deduced.
The resultant similarity score is then compared with a
certain threshold in order to decide the match result:
authentication OK (both prints come from the same finger)
or authentication NOK (both prints come from different
IV. HARDWARE-SOFTWARE CO-DESIGN
Hardware-software co-design methodology for hardware-
software based systems is a well-known technique in the
current technological age. Biometrics field is not an
exception, a proof of this is the big amount of biometric
matcher or authenticator systems available nowadays in the
market . However, the emphasis of this work is the
implementation of biometric systems by making use of
reconfigurable architectures. This novel approach benefits
the reuse of hardware sources in order to obtain embedded
systems with similar performance, but with higher
flexibility and at lower cost than current systems.
A. Physical Platform
implementations of complete hardware/software systems
within a single chip. A new trend in system-on-chip design
are the System Level Integrated Circuits, which consist of a
microprocessor, program and data memory, various
peripherals, and a programmable system logic, providing
thus a reduced but reconfigurable architecture to develop
any kind of application.
Many reconfigurable FPGAs already exist in the market
. Among them, authors have selected the system-on-chip
FPSLIC from Atmel. The platform developed in this work
is based on FPSLIC device and a configuration EEPROM
The FPSLIC (Field Programmable System Level
microprocessor, its memory block (36 kbytes of
program and data memory), some peripherals such as
three programmable timers, two serial UART, one
I2C controller, one 8-bit hardware multiplier
module, as well as two I/O ports, and a 40-kgates
FPGA with dynamic reconfigurability performance,
all embedded in a SRAM-based monolithic field
The EEPROM memory is used for 2 main purposes:
a) as configuration memory, in order to store the
design that has to be downloaded into the FPSLIC
technology allows customized
incorporates one 8-bit
on power-up or at any moment during execution
b) as non-volatile memory, used to store those
application specific data such as user’s fingerprint
templates or other configuration parameters needed.
The suggested embedded system allows the hardware-
software co-design of the application. The design is stored
in the form of bitstream, which includes the FPGA
hardware content, the microprocessor program code and the
application data. It is possible to partition the application in
hardware and software tasks, thus synthesizing in the FPGA
those computationally expensive tasks, whereas the
microprocessor is in charge of executing the rest of less
complex tasks and managing also the reconfiguration of the
B. Hardware-Software Partitioning
It is assumed that template and input minutiae sets have
been already stored into the system, in enrolment and
authentication stages respectively, before starting the match
In order to partition the matching algorithm in hardware
and software tasks, a first implementation of the complete
algorithm uniquely by software is done. From here, those
more expensive tasks are identified to be implemented as
hardware tasks. Thus the microprocessor is responsible for
managing the matching process whereas in the FPGA the
local and global analysis of both minutiae sets are
implemented. Several computational coprocessors have
been synthesized into the FPGA, all of them controlled by
means of a hardware FSM (finite state machine) core block,
responsible for managing the hardware tasks under pipeline
A CORDIC coprocessor  has been synthesized
in order to accelerate the computation of distances
(SQRT function) and angles (ATAN function)
between minutia points.
A DMA controller has been implemented in order to
provide access to the memory in a fast way, without
the support of the microprocessor.
Some configuration registers have been synthesized
on the FPGA to allow the microprocessor to control
and monitor the hardware processing.
The application block diagram is shown in Fig. 6.
Fig. 6. Fingerprint matching application block diagram.
C. Reconfigurable Hardware Stages
Owing to the limited hardware resources available in the
current FPGA, and the computational overhead present
during local and global minutiae analysis, FPGA run-time
reconfiguration has been needed in order to increase the
effective functional density of the current design. The
matching algorithm has been split in two stages: the first
one is based on the local analysis of both minutiae sets,
whereas in the second stage the global analysis is computed.
Several hardware blocks have been implemented in every
stage on the FPGA, and a complete reconfiguration of the
FPGA has been needed between both stages to fulfil the
The application flow diagram is shown in Fig. 7.
Fig. 7. Fingerprint matching application flow diagram.
V. EXPERIMENTAL RESULTS
There exists a trade-off between cost and execution time
when performing the hardware-software partitioning of the
application. Hardware (FPGA-based) implementation tasks
mean more cost whereas software (microprocessor-based)
implementation tasks mean
reconfigurability performance of the selected FPGA allows
to further reduce the cost of hardware implementation,
whereas it increases as penalty the extra load (time and/or
resources) required for reconfiguration purposes. Finally,
the application requirements are the basis to perform an
summarizes the experimental results reached in this work.
Although the overall application timing is not minimal –
due to several factors such as the working frequency
restrictions in current FPGA and CPU devices–, the results
shown on Table 1 points the feasibility of the novel
architecture presented in this work. In those applications
where the overhead due to the FPGA reconfiguration is not
critical (6.2% of the total time in our application), this
topology can be used in order to save FPGA resources, thus
more latency. The
partitioning. Table 1
Template MinutiaeInput Minutiae
Local AnalysisLocal Analysis
C.F. Pair Selection
Global AnalysisGlobal Analysis
FPGA Context 1
FPGA Context 2
HW Tasks SW Tasks
reducing cost without having a negative effect on final
EEPROM memory (bytes)
Data memory (bytes)Memory
Code memory (bytes)
Percent load CPU (%)
Percent load FPGA (%)
# Gates context 1
# Flip Flops context 1
# Gates context 2
# Flip Flops context 2
Task 1 (Sw) Minutiae set up
Task 2 (Hw) Template local analysis
Task 3 (Hw)Input local analysis
Task 4 (Sw)Central feature selection
Task 5FPGA Reconfiguration
Task 6 (Hw)Template global analysis
Task 7 (Hw) Input global analysis
Task 8 (Sw) Matching result computation
Total execution time (typical value):
VI. CONCLUSIONS AND FUTURE WORK
Current personal biometrics-based recognition systems
deal with unlimited computational platforms based on high
performance microprocessors with big amounts of memory
resources and powerful DSP processors running parallel
tasks at high speed. Despite this, current performance of
software-based solutions is not enough to satisfy low-cost
A novel system architecture for a fingerprint
authentication system based on hardware-software co-
design has been proposed in this paper. In comparison with
conventional architectures, the suggested topology is based
on a general-purpose microcontroller and a small-size
reconfigurable FPGA used as hardware accelerator
integrated into the system. The FPGA gives additional
flexibility and increases the workload capability of the
platform by downloading functions to the FPGA as they are
needed, and reconfiguring it along the process.
The physical implementation of the fingerprint matching
stage has been discussed in this work. It has been proven
that it is possible to implement a fingerprint matching
system by using the proposed system architecture.
The aim of the authors in their future work is to take
profit of the advantages of FPGA reconfigurability
performance in order to develop all the steps involved in the
recognition process: not only the fingerprint matching step,
but also the fingerprint acquisition process, the image
enhancement stage and the feature extraction phase.
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Mariano Fons received his B.S.
degree in electrical engineering
from Rovira i Virgili University
in 1995, and his M.S. degree in
Rovira i Virgili University in
2001. He is currently a Ph.D.
student in the Department of Electronic, Electrical and Automation
Engineering at the Rovira i Virgili University. His current research
interests include hardware-software co-design techniques and VLSI
implementations of embedded systems.
Francisco Fons received his B.S.
degree in electrical engineering
and his M.S.
Rovira i Virgili University,
Tarragona (Spain) in 1995 and
2001, respectively. He is currently pursuing a Ph.D. degree from Rovira i
Virgili University in the field of VLSI design methodologies and
dynamically reconfigurable hardware techniques for embedded systems.
assistant professor at the Rovira i
Virgili University, Tarragona
(Spain). He received his Ph.D.
degree in 2001, and he has been
several European and Spanish
Cantó works as
research projects about reconfigurable devices, smart card architectures,
and fingerprint coprocessors.