Thermal phenomena in deeply scaled MOSFETs

Abstract

Thermal phenomena are having an increasing influence on drive and leakage currents in modern transistors. This trend is accelerated for confined-geometry devices, which include thermally-resistive interfaces and materials with low thermal conductivity (e.g. SiO₂, Si _1-xGe_x). This paper summarizes the nanotransistor thermal design challenges and reviews the latest advancements in electro-thermal modeling

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Thermal Phenomena in Deeply Scaled MOSFETs

Jeremy Rowlette1, Eric Pop1, Sanjiv Sinha2,3, Mathew Panzer2, and Kenneth Goodson2

Depts. of 1Electrical and 2Mechanical Engineering, Stanford University, Stanford, CA and 3Intel Corporation, Hillsboro, OR
Contact: rowlette@stanford.edu, Bldg 530 Room 101, Stanford CA 94305-3030, tel 650.725.3314

Abstract- Thermal phenomena are having an increasing influ-
ence on drive and leakage currents in modern transistors. This
trend is accelerated for confined-geometry devices, which
include thermally-resistive interfaces and materials with low
thermal conductivity (e.g. SiO2, Si1-xGex). This paper summa-
rizes the nanotransistor thermal design challenges and re-
views the latest advancements in electro-thermal modeling.

Introduction

Within the last decade, there has been growing concern with
thermal phenomena occurring on the microprocessor, includ-
ing interconnect and via self-heating. Self-heating of modern
transistors has received increased attention as an important
consideration for simulations at the device and circuit levels.
Dynamic power dissipation in nanotransistors will not be
significantly reduced by device scaling and the volumetric
heat generation density will therefore rise sharply each gen-
eration. The dynamic power of digital logic circuits based on
nanotransistor technologies scales roughly as CeffVdd
the effective capacitance (Ceff) includes significant contribu-
tions from the interconnects. The square-law dependence on
the operating voltage (Vdd) appears to offer the strongest lever
for reducing dynamic power. However, a reduction in Vdd
would require a comparable decrease in threshold voltage
(Vt) in order to maintain drive current. The threshold voltage
cannot be arbitrarily reduced since source-drain leakage gen-
erally grows exponentially with reductions in Vt [1]. A trade-
off between performance and power consumption naturally
ensues with the threshold voltage acting as the central pa-
rameter in optimization. As a consequence of this tradeoff,
Vdd and Vt have historically scaled slowly in comparison to
the physical dimensions of devices. This long-term trend has
led to stronger electric fields and rapidly increasing power
densities [2] to the extent that major shifts in process design,
performance targets, and architecture are now necessary [3].
Even with a slower projected trend in frequency scaling, only
modest reductions in Vdd are expected. Therefore, volumetric
power density of nanotransistors will continue to grow rap-
idly with each process generation and will be compounded by
shifts towards confined geometry devices.
Leakage power and its relationship to thermal transport
should receive more attention in future device design. A key
characteristic difference between leakage and dynamic power
consumption should be made clear at this point. Unlike dy-
namic power, leakage power tends to increase with junction
temperature, which implies that an increase in either power or
thermal resistance will cause further increases in leakage
power consumption by means of positive feedback [4]. As
frequencies and power densities increase, a greater fraction of
2f, where
the heat generated during device switching persists in the off
state, increasing total leakage. Furthermore, the device per-
formance, e.g. the CV/I metric, is a relatively weak function
of device temperature compared to that for leakage [1].

Heat Generation and Conduction

Electrons accelerate in the electric field and heat the lattice
through electron-phonon scattering (Fig. 1) at a total rate pro-
portional to the familiar macroscopic power relation: P=I•V.
Nanoscale transistors require greater attention to high-
electric-field, ballistic, and quantum phenomena, both for the
electron and phonon systems and for proper description of
their interaction. As device channel lengths decrease below
50 nm, a simulation approach deliberately incorporating elec-
tron-phonon scattering and the complete dispersion character-
istics of each particle type becomes more relevant. Further-
more, it becomes important to track the detailed populations
of phonons generated by electron scattering, since the phonon
distribution function strongly influences the ability of heat to
conduct away from the device.
In deeply-scaled transistors, energy is transferred to the
phonon system within about 50 nm of the highly localized
(~10 nm) electric field region centered near the channel-drain
boundary [5]. Energy is then carried out to the contacts and
package boundaries primarily by means of acoustic phonon
propagation. Resistance to acoustic phonon transport by scat-
tering with other phonons, impurities, and boundaries leads to
increases in the phonon population within the device, which
can be described using a higher effective temperature (Teff)
[6]. Phonon occupation (N=1/(exp(ħω/kBTeff)-1) directly af-
fects the electron-phonon scattering rates which are propor-
tional to (N + ½ ± ½), where the signs correspond to phonon
emission (+) and absorption (-) processes, respectively [7].
Phonon scattering influences the electron transport in two
important ways. First, the effective mobility is reduced, lead-
ing to lower drive currents. Second, phonon absorption near
the source-channel boundary can lead to increased electron
injection efficiency. The second effect can enhance device
performance in the on state by increasing drive current but
can also increase subthreshold leakage in the off state.
Boundary scattering will be a major source of thermal re-
sistance in future low-dimensional devices such as FinFETs
[8,9]. Although bulk silicon has a high intrinsic thermal con-
ductivity, the effective thermal conductivities of ultra-thin
silicon films are severely reduced (~10x) by phonon bound-
ary scattering [10,11]. Furthermore, such devices routinely
use SiO2 or other low intrinsic thermal conductivity materials
to electrically isolate the active regions of the device. An
electro-thermal optimization, which incorporated boundary
0-7803-9269-8/05/$20.00 (c) 2005 IEEE

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scattering and thermal resistances of the surrounding me-
dium, was performed by Pop et al. for a raised S/D thin body
FET with sub-35 nm channel lengths [11]. It was shown that
the benefits of increasing the S/D layer thickness in order to
improve heat conduction was countered by the associated
increases in capacitive coupling to the gate (Fig. 2). An opti-
mal S/D layer thickness was found to be about 3-4x the body
thickness. As the spatial density of interfaces increases with
the reduction of device dimensions, heat transport across
boundaries will play an increasing role in determining the
overall thermal properties of the device [6]. For example, the
thermal interface resistance associated with a metal-oxide-
silicon stack was shown to be equivalent to the thermal resis-
tance of ~20 nm of oxide [12]. The development of accurate
boundary resistance models has proven to be extremely diffi-
cult and is still the subject of active research today [13-15].
Within 10’s of nanometers of the heat source, neither
charge nor heat energy transport is diffusive in nature.
Rather, electrons and phonons propagate under near-ballistic
conditions leading to highly non-equilibrium distributions for
each carrier type. The Boltzmann transport equation (BTE)
can be solved to obtain accurate distribution profiles for each
particle type provided that certain quantum phenomena can
be neglected [7]. Significant progress has been made in the
detailed modeling of independent electron and phonon trans-
port processes in silicon devices by solving various limiting
forms of the BTE (e.g., Refs. [6, 16, 17]). A rigorous solu-
tion to the electron BTE (e-BTE) was performed in Ref. [18]
using an electron Monte Carlo (e-MC) technique optimized
for calculating phonon generation rates (spectra) in silicon
devices, which included optical and acoustic phonon disper-
sion. Detailed simulations [19] showed that ~2/3 of the heat
generation occurred in the optical phonon branches for elec-
tric field strengths typical of modern transistors. However,
despite receiving a majority of the energy during hot carrier
relaxation in the drain, optical phonons have essentially no
contribution to heat transport because their group velocities
are small compared to those of the long wavelength acoustic
modes. Understanding the decay processes of optical phonons
into the heat conducting acoustic modes is therefore an essen-
tial aspect of electro-thermal device modeling at nanoscales.
A recent molecular dynamics study by Sinha et al. [20] of-
fered crucial insight into the decay processes of the interval-
ley g-type longitudinal optical phonons (g-LO). Phonons cen-
tered around the g-LO mode in k-space (~0.3 of the distance
to the edge of the Brillouin zone) are of special interest be-
cause they scatter strongly with hot electrons and have a rela-
tively low density-of-states, characteristics which lead to hot
phonon behavior [5, 21]. Determining the dependence of op-
tical phonon lifetimes on power density is also of great inter-
est to electro-thermal modeling of realistic devices. Because
of a lack of experimental data, most optical phonon lifetime
parameters used in phonon transport models rely exclusively
on optical Raman data and calculations where there is a
wealth of knowledge spanning decades of research [22-24].
For equilibrium conditions near 300 K, Raman mode life-
times have been reported to be around 4 ps [22] and are ex-
pected to decrease with increasing local power density [20].

Coupled Electrical and Thermal Simulations

Despite significant advances in independent transport simula-
tions, self-consistent electro-thermal simulations in the sub-
continuum regime (< 100 nm) are very limited in number and
in scope. Nearly a decade ago, Lai and Majumdar [25] devel-
oped a coupled hydrodynamic solution separating the optical
and acoustic phonon branches. Recently, Sinha et al. [26]
introduced a computationally efficient split-flux solution to
the phonon BTE (p-BTE), which captures ballistic phonon
conduction near the nanometer-sized heat source and yields a
convenient interface to continuum calculations far from the
heat source. Using the detailed phonon generation rates cal-
culated by e-MC in Ref. [19] the split-flux p-BTE model was
used to simulate 2-D steady-state and 1-D transient heating
inside of an 18 nm depleted substrate SOI device (Figs. 3 and
4) [26]. Most recently, we have performed steady-state, self-
consistent, coupled, electron-phonon transport simulations of
an isolated, bulk, 20 nm, n+/n/n+ silicon device (Figs. 5-7)
[27] by combining the e-MC presented in Ref. [18] with the
split-flux p-BTE method presented in Ref. [26]. The impact
of self-heating for the n+/n/n+ device was studied for three
different voltages, the results of which are summarized in
Figs. 8-10. Results showed an effective lattice temperature
rise as high as ~50 K with respect to the reference tempera-
ture (300 K) at the device contacts for the 1.0 V bias condi-
tion. For such a temperature rise, it was found that current
was reduced by only 2.2%. In a more-realistic thin-body de-
vice structure, phonon boundary scattering would act to in-
crease the effective thermal resistance of the device by about
an order of magnitude. Neglecting the strong negative feed-
back on electron transport that would occur, such an increase
in thermal resistance would lead to projected temperature
rises of ~10x that which was calculated for the bulk device.

Conclusion

We have reviewed the recent progress in electro-thermal
simulation of advanced silicon devices. We have examined
the effects of boundary and interface scattering as well as
non-equilibrium ballistic transport on charge and heat con-
duction inside of deeply scaled MOSFETs. Recent work has
culminated in the demonstration of self-consistent, electron-
phonon simulations using an electron Monte Carlo technique
and a split-flux form of the phonon BTE. It is apparent that
the small, restricted dimensions of future devices will affect
both current and heat transport, while thermal cross-talk is
expected to be of significance between closely packed de-
vices, device fins or nanowire/tube segments.

Acknowledgments

This work was supported by the Semiconductor Research Corpo-
ration (SRC) Task 1043.

Page 3

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Lex




Figure 1. Time scales for various energy transfer
processes between the electrons and lattice phonons in
silicon. The most appropriate optical phonon lifetime
values to use in simulating nanometer scale devices
under typical operating conditions remains to be fully
answered. Ref. 20 offers insight into this question in
the framework of molecular dynamics simulations.





Figure 2. Electro-thermally self-consistent comparative study of “well-behaved” ultra-thin body SOI and germanium-on-insulator (GOI) devices with 18
nm channel lengths [11]. A larger (e.g. elevated) source and drain design will alleviate S/D series resistance and heat dissipation problems, but eventually
lead to an increase in parasitic capacitance which reduces the intrinsic speed gain.




Figure 3. Effective temperature contours of an 18 nm fully depleted
SOI FET calculated using a split-flux solution to the phonon BTE [26].

Figure 4. Transient phonon transport simulations with periodic 10 ps
current pulses. The transverse acoustic (TA), longitudinal acoustic
(LA) and longitudinal optical (LO) phonon branches are tracked [26].
tSD
tbody
Intrinsic Delay (ps)
tSD= ntbody
n = 1... 5
CV/I
Gate Length Lg(nm)
18 nm
TA
LA
LO
Phonon Occupation (N)
1-10 ps
Time [ps]

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Figure 5. Current density (left axis) and peak electric field (right axis)
vs. source-drain bias voltage (V) for a 1-D n+/n/n+ silicon diode mod-
eled using self-consistent e-MC/split-flux p-BTE technique discussed in
the text and in Ref. [27].

Figure 6. Electron potential energy vs. position within the n+/n/n+ device
with electrical characteristics shown in Fig. 5 for three bias conditions.
The device has three regions: two 150 nm n+ (1020 cm-3) source and drain
regions separated by a 20 nm n-type (1016 cm-3) “channel”. The doping is
uniform in each region with a 1.25 nm/decade roll-off between regions.

Figure 7. Zoomed-in view of the potential energy barrier seen by source
electrons for the 0.6 V bias condition. Quantum transport effects (e.g.
tunneling) were not included in this work, but will become more impor-
tant as the barrier reduces in height and width.

Figure 8. Volumetric power generation rate vs. position [5] within the 1-D
n+/n/n+ device. The power generation at each grid point was computed by
adding the appropriately weighted phonon emission events and subtracting
the phonon absorption events and dividing by the simulation time interval.

Figure 9. Effective lattice temperature (Teff) computed using the self-
consistent e-MC/split-flux p-BTE technique described in the text [27].

Figure 10. Effect on average source injected electron energy using the
self-consistent e-MC/split-flux p-BTE technique described in the text [27].
n+ (1020 cm-3)
n (1016 cm-3)
1.0 V
0.8 V
0.6 V
80 meV
VSD = 0.6 V 1.0 V
0.8 V
0.6 V
1.0 V
0.8 V
0.6 V
Coupled
Uncoupled
n+n+
n
~e-x/20nm
VSD = 1.0 V
Diffusive
conduction