Conference Paper

High performance 5nm radius Twin Silicon nanowire MOSFET(TSNWFET): Fabrication on bulk Si wafer, characteristics, and reliability

Device Res. Team, Samsung Electron. Co., Gyeonggi-Do
DOI: 10.1109/IEDM.2005.1609453 Conference: Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International
Source: IEEE Xplore

ABSTRACT For the first time, we have successfully fabricated gate-all-around twin silicon nanowire transistor (TSNWFET) on bulk Si wafer using self-aligned damascene-gate process. With 10nm diameter nanowire, saturation currents through twin nanowires of 2.64 mA/mum, 1.11 mA/mum for n-channel TSNWFET and p-channel TSNWFET are obtained, respectively. No roll-off of threshold voltages, ~70 mV/dec. of substhreshold swing (SS), and ~20 mV/V of drain induced barrier lowering(DIBL) down to 30 nm gate length are observed for both n-ch and p-ch TSNWFETs

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Available from: Jong-Bong Park, Oct 27, 2014
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