Conference Proceeding

A 0.65V CMOS power amplifier for biotelemetry applications

Dept. of Electr. & Comput. Eng., McMaster Univ., Hamilton, Ont.
Canadian Conference on Electrical and Computer Engineering 06/2005; DOI:10.1109/CCECE.2005.1557204 In proceeding of: Electrical and Computer Engineering, 2005. Canadian Conference on
Source: IEEE Xplore

ABSTRACT In order to reduce the power consumption in biomedical implantable electronic systems, there is a major demand on reducing the supply voltage. This paper presents a fully integrated, 650 MHz class-E power amplifier (PA), with a class-F driver stage that is suitable for low-voltage operation. The circuit was fabricated in a standard 0.18 mum CMOS technology. Measurement results show a maximum drain efficiency of 15% and a maximum gain of 11.5 dB. When operated from a 0.65 V supply, the PA delivers an output power of 750 muW with a maximum power-added efficiency (PAE) of 10%. The circuit also has a second output to test the effects of using an on-chip filter in low-power designs. This work demonstrates the feasibility of using class-E PAs for short-range, low-power applications

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Keywords

650 MHz class-E power amplifier
 
biomedical implantable electronic systems
 
class-E PAs
 
class-F driver stage
 
feasibility
 
low-power applications
 
low-power designs
 
low-voltage operation
 
major demand
 
maximum gain
 
maximum power-added efficiency
 
on-chip filter
 
output power
 
paper presents
 
power consumption
 
standard 0.18 mum CMOS technology