Conference Paper

Architectural issues in base-station frequency synthesizers

Dept. of Electr. Eng., Univ. of Washington, Seattle, WA, USA
DOI: 10.1109/ISCAS.2005.1466015 Conference: Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Source: IEEE Xplore

ABSTRACT Base station frequency synthesizers have extremely stringent specifications in terms of low integrated RMS phase error and low lock time. Satisfying both these conflicting specifications demands the selection of the right architecture. At the same time, other significant issues, such as spur suppression and tuning range, necessitate the use of allied techniques. The different architectural choices available for this application are compared vis-a`-vis their respective benefits and drawbacks. A dual-loop-PLL-based architecture that meets very strict specifications is designed and simulated at 2 GHz. This synthesizer has an integrated RMS phase error of 1° while having a phase noise of -120 dBc/Hz at 600 kHz offset. The lock time is 40 μs, and the tuning range is 100 MHz.

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