Conference Paper

A fixed-point 3D graphics library with energy-efficient cache architecture for mobile multimedia systems

Korea Advanced Institute of Science and Technology, Sŏul, Seoul, South Korea
DOI: 10.1109/ISCAS.2005.1465657 Conference: Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Source: IEEE Xplore


A 3D computer graphics (3DCG) library with energy-efficient cache architecture is implemented for mobile multimedia systems. The developed library is based on fixed-point arithmetic for low energy consumption. To achieve high performance, the library is optimized at both the assembly and the algorithm levels on 3 different advanced RISC machine (ARM) processors. In order to enhance energy-efficiency as well as performance, a series of simulations have been performed on application programs with various cache configurations. We find that a 2-way set associative cache consumes low energy with negligible performance degradation. In this cache system, the optimized library can achieve 66.1% performance improvement and 25.3% energy saving on average compared with the conventional 4-way set associative cache system. Software and hardware co-optimization achieves 67 K polygons/s with low energy consumption. We verified the graphics library with proposed cache architecture by implementing a mobile graphics LSI.

21 Reads
  • Source
    • "Fig. 8 shows the simulation results of RSB mapping. In a typical 3-D application, the RSB mapped texture cache shows average of 0.4% miss rate and the power consumption is reduced by 17.4% compared to 8x8 block mapped texture cache [5]. "
    [Show abstract] [Hide abstract]
    ABSTRACT: A 1.2Mpixles/s/mW 3D rendering processor is designed and implemented for portable multimedia application. A sustained 20Mpixels/s pixel fill rate is obtained at 10MHz with the help of embedded depth buffer and recursive sub-block mapped texture cache. In order to achieve low power rendering operation, SlimShader architecture with non-atomic read-modify-write scheme and logarithmic datapath is employed. The rendering processor consists of 281k logic gates and 164kB embedded SRAM in 25mm<sup>2</sup>. It is fabricated in 0.18mum 1-poly 6-metal CMOS logic process and real-time 3D graphics images are successfully demonstrated on the system evaluation board. It consumes 17mW at 10MHz while drawing texture-mapped 3D graphics images
    Asian Solid-State Circuits Conference, 2005; 12/2005
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: Low-power three-dimensional (3-D) graphics rendering engine with lighting acceleration is designed and implemented for handheld multimedia terminals. The lighting unit is hardware implemented and integrated into the chip for the low-power acceleration of the 3D graphics applications. We adopt the following three steps to handle the memory bandwidth problem for rendering operations. I) We find bilinear MIPMAP is the best texture filtering algorithm for handheld systems based on our developed energy-efficiency metric. With this observation, we adopt bilinear MIPMAP for our texture filtering unit, which requires only 50% of texture memory bandwidth compared with trilinear MIPMAP filtering. II) We put the depth test operation into the earlier stage of the graphics pipeline, which eliminates texture memory accesses for invisible pixels. III) We develop a power-efficient small cache system as the interface to rendering memory. The accelerator takes 181 K gates and the performance reaches 20 Mpixels/s. A test chip is implemented with 1-poly 6-metal 0.18 μm CMOS technology. It operates at the frequency of 20 MHz with 14.7 mW power consumption.
    IEEE Transactions on Consumer Electronics 09/2005; 51(3-51):1020 - 1027. DOI:10.1109/TCE.2005.1510517 · 1.05 Impact Factor

Similar Publications


21 Reads
Available from