Advanced wafer bonding solutions for TSV integration with thin wafers
ABSTRACT Due mainly to the thermal budget of CMOS devices, bonding techniques compatible with CMOS processing are limited to direct oxide bonding, metal bonding, adhesive bonding, and various hybrids of those methods. In order to facilitate thin wafer processing with existing fab equipment, we developed total solutions for temporary bonding and debonding of carrier wafers. When it comes to TSV integration, the temporary bonding process based on a spin-on adhesive is becoming the industry standard over that with a lamination tape due to better edge protection, compatibility with topographic surfaces, and better stability at higher process temperatures. The benefits with a newly developed spin-on process include temperature stability over 250degC, compatibility with bumped surfaces, short debonding time, easy thermal release, slide-off debonding, and easy cleanup with polar solvents. It is being proven that our temporary bonding and debonding techniques offer time and cost efficiency for TSV integration processes utilizing existing and established equipment and technologies. For aligned wafer-to-wafer (W2W) bonding, we developed multiple direct and indirect bond alignment methods to stack various types of substrates as well as improve alignment accuracy with minimal z-axis movement. SmartViewreg alignment enables the use of any unique features on the front-side of non-IR transparent wafers for face-to-face bonding while maintaining sub-micron post-bond alignment accuracy. EVG's unique bonding processes and equipment are being widely evaluated and adopted for various TSV applications. For instance, blanket CuCu bonding performed at 415degC and 25 kN for 40 min showed neither bond interface nor voids with the quantitative post-bond adhesion energy of 10.4 J/m2. The post-bond alignment accuracy of less than 1 mum (3sigma) was also achieved with Cu patterned wafers. Chip-to-wafer (C2W) bonding, based on the thermocompression bonding mechanisms such as Cu-pol-
ymer hybrid or Cu-Sn intermetallic compounds (IMC), is needed for future heterogeneous stacking. We developed a new advanced chip-to-wafer (AC2W) bonding concept for higher throughput and lower cost-of-ownership (CoO). The temporary pre-bonding is performed on a pick-and-place machine, followed by the permanent bonding of dies to a device wafer as a batch process in a specially designed bond chamber. A true known-good-die (KGD) stacking can be achieved through the control of the center position, the absolute value and the direction of the applied force. The average displacement with Cu-Sn-Cu bonding was 1.5 mum with the chip-to-chip deviation of 2.7 mum (3sigma).
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ABSTRACT: This paper presents a review of the wafer-to-wafer alignment used for 3-D integration. This technology is an important manufacturing technique for advanced microelectronics and microelectromechanical systems, including 3-D integrated circuits, advanced wafer-level packaging, and microfluidics. Commercially available alignment tools provide prebonding wafer-to-wafer misalignment tolerances on the order of 0.25 μm. However, better alignment accuracy is required for increasing demands for higher density of through-strata vias and bonded interstrata vias, whereas issues with wafer-level alignment uniformity and reliability still remain. Three-dimensional processes also affect the alignment accuracy, although the misalignment could be reduced to certain extent by process control. This paper provides a comprehensive review of current research activities over wafer-to-wafer alignment, including alignment methods, accuracy requirements, and possible misalignments and fundamental issues. Current misalignment concerns of the major bonding approaches are discussed with detailed alignment results. The fundamental issues associated with wafer alignment are addressed, such as alignment mechanisms, uniformity, reproducibility, thermal mismatch, and materials. Alternative alignment approaches are discussed, and perspectives for wafer-to-wafer alignment are given.Journal of Microelectromechanical Systems 09/2011; · 2.13 Impact Factor
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ABSTRACT: In 3D integration package using TSV technology, bonding is the core technology for stacking and interconnecting the chips or wafers. During bonding process, however, warpage and high stress are introduced, and will lead to the misalignment problem between two chips being bonded and failure of the chips. In this paper, a finite element approach is used to predict the warpages and stresses during the bonding process. In particular, in-plane deformation which directly affects the bonding misalignment is closely analyzed. Three types of bonding technology, which are Sn-Ag solder bonding, Cu-Cu direct bonding and SiO2 direct bonding, are compared. Numerical analysis indicates that warpage and stress are accumulated and become larger for each bonding step. In-plane deformation is much larger than out-of-plane deformation during bonding process. Cu-Cu bonding shows the largest warpage, while SiO2 direct bonding shows the smallest warpage. For stress, Sn-Ag solder bonding shows the largest stress, while Cu-Cu bonding shows the smallest. The stress is mainly concentrated at the interface between the via hole and silicon chip or via hole and bonding area. Misalignment induced during Cu-Cu and Sn-Ag solder bonding is equal to or larger than the size of via diameter, therefore should be reduced by lowering bonding temperature and proper selection of package materials.Journal of the Korean Society for Precision Engineering. 01/2012; 29(5).
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ABSTRACT: In this paper the integration challenges related to oxide-oxide bonding for wafer-to-wafer stacking technology are discussed. Furthermore, interface defectivity, wafer-to-wafer alignment and bond strength data are presented.IEEE International Conference on 3D System Integration, 3DIC 2010, Munich, Germany, 16-18 November 2010; 01/2010