Article

Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM

Center for Integrated Circuits & Syst. (CICS), Nanyang Technol. Univ., Singapore, Singapore
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (Impact Factor: 1.22). 03/2011; DOI: 10.1109/TVLSI.2009.2033110
Source: OAI

ABSTRACT A new current-mode sense amplifier is presented. It extensively utilizes the cross-coupled inverters for both local and global sensing stages, hence achieving ultra low-power and ultra high-speed properties simultaneously. Its sensing delay and power consumption are almost independent of the bit- and data-line capacitances. Extensive post-layout simulations, based on an industry standard 1 V/65-nm CMOS technology, have verified that the new design outperforms other designs in comparison by at least 27% in terms of speed and 30% in terms of power consumption. Sensitivity analysis has proven that the new design offers the best reliability with the smallest standard deviation and bit-error-rate (BER). Four 32 × 32-bit SRAM macros have been used to validate the proposed design, in comparison with three other circuit topologies. The new design can operate at a maximum frequency of 1.25 GHz at 1 V supply voltage and a minimum supply voltage of 0.2 V. These attributes of the proposed circuit make it a wise choice for contemporary high-complexity systems where reliability and power consumption are of major concerns.

0 Bookmarks
 · 
344 Views
  • [Show abstract] [Hide abstract]
    ABSTRACT: A digitized replica bitline delay technique has been proposed for random-variation-tolerant timing generation of static random access memory (SRAM) sense amplifiers (SA). The timing variation of SA attributable to the random variation of transistor threshold voltage (V<sub>TH</sub>) is reduced by a sufficient count of replica cells, and replica bitline delay is digitized and multiplied to adjust it to the target timing for SA. The variation of the generated timing was 41% smaller than that with a conventional technique and cycle time was reduced 20% at the supply voltage (V<sub>DD</sub>) of 0.6 V in 40 nm CMOS technology with this scheme.
    IEEE Journal of Solid-State Circuits 12/2011; · 3.06 Impact Factor
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: Sense amplifiers are one of the most vital circuits in the margin of CMOS memories. Their performance influences both memory access time and overall memory power dissipation. The existing Current-Mode Sense Amplifier coupled with a simplified read-cycle-only memory system has the ability to quickly amplify a small differential signal on the Bit-Lines (BLs) and Data-Lines (DLs) to the full CMOS logic level without requiring a large input voltage swing. The Current-Mode Sense Amplifier has two levels of sensing schemes. This hierarchical two-level sensing scheme helps in reducing both power consumption and sensing delay imposed by the bit-lines and the data-lines on high density SRAM designs. This type of Current-Mode Sense Amplifier improves the sensing speed and reliability of the previously published designs and at the same time reduces the power consumption to a considerable extent. In order to further improve the performance of the existing current-mode sense amplifier, an efficient current-mode sense amplifier is proposed in this research. The proposed research work uses the clamped bit-line sense amplifier.
    01/2012;

Full-text (3 Sources)

Download
86 Downloads
Available from
May 17, 2014