Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM

Center for Integrated Circuits & Syst. (CICS), Nanyang Technol. Univ., Singapore, Singapore
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (Impact Factor: 1.36). 03/2011; 19(2):196 - 204. DOI: 10.1109/TVLSI.2009.2033110
Source: IEEE Xplore


A new current-mode sense amplifier is presented. It extensively utilizes the cross-coupled inverters for both local and global sensing stages, hence achieving ultra low-power and ultra high-speed properties simultaneously. Its sensing delay and power consumption are almost independent of the bit- and data-line capacitances. Extensive post-layout simulations, based on an industry standard 1 V/65-nm CMOS technology, have verified that the new design outperforms other designs in comparison by at least 27% in terms of speed and 30% in terms of power consumption. Sensitivity analysis has proven that the new design offers the best reliability with the smallest standard deviation and bit-error-rate (BER). Four 32 × 32-bit SRAM macros have been used to validate the proposed design, in comparison with three other circuit topologies. The new design can operate at a maximum frequency of 1.25 GHz at 1 V supply voltage and a minimum supply voltage of 0.2 V. These attributes of the proposed circuit make it a wise choice for contemporary high-complexity systems where reliability and power consumption are of major concerns.

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    • "This paper presents a current-mode SA that improves the sensing speed and reliability of the previously published designs and at the same time reduces the power consumption. It was extensively simulated and graphically presented in comparison with other widely used SA topologies, namely the high-speed [11], decoupled latch [5], [6], the alpha latch [7] designs and read only memory system [1] designs. "
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    ABSTRACT: Sense amplifiers are one of the most vital circuits in the margin of CMOS memories. Their performance influences both memory access time and overall memory power dissipation. The existing Current-Mode Sense Amplifier coupled with a simplified read-cycle-only memory system has the ability to quickly amplify a small differential signal on the Bit-Lines (BLs) and Data-Lines (DLs) to the full CMOS logic level without requiring a large input voltage swing. The Current-Mode Sense Amplifier has two levels of sensing schemes. This hierarchical two-level sensing scheme helps in reducing both power consumption and sensing delay imposed by the bit-lines and the data-lines on high density SRAM designs. This type of Current-Mode Sense Amplifier improves the sensing speed and reliability of the previously published designs and at the same time reduces the power consumption to a considerable extent. In order to further improve the performance of the existing current-mode sense amplifier, an efficient current-mode sense amplifier is proposed in this research. The proposed research work uses the clamped bit-line sense amplifier.
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    ABSTRACT: Based on the characteristics of current-mode circuits, which can easily realize arithmetic operations, the threshold arithmetic operation and the nonnegative operation are defined in this paper, and the threshold-arithmetic algebraic system suitable to design current-mode circuits is established. Then, HE map is defined and used as the graphic representation of threshold-arithmetic functions, and the method of converting traditional logic function to threshold-arithmetic function with HE Map is expounded. At last, the design method of multiple-valued I'L circuits based on threshold arithmetic algebraic system and HE map is proposed. The HSPICE simulation results using TSMC 0.18μm technology show that the designed I'L circuits have the correct functions. The threshold arithmetic algebraic system is a new simple and effective method for designing the current-mode circuits.
    Electronics, Communications and Control (ICECC), 2011 International Conference on; 01/2011
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    ABSTRACT: Based on multi-valued logic, adiabatic circuits and the structure of ternary static random access memory (SRAM), a design scheme of a novel ternary clocked adiabatic SRAM is presented. The scheme adopts bootstrapped NMOS transistors, and an address decoder, a storage cell and a sense amplifier are charged and discharged in the adiabatic way, so the charges stored in the large switch capacitance of word lines, bit lines and the address decoder can be effectively restored to achieve energy recovery during reading and writing of ternary signals. The PSPICE simulation results indicate that the ternary clocked adiabatic SRAM has a correct logic function and low power consumption. Compared with ternary conventional SRAM, the average power consumption of the ternary adiabatic SRAM saves up to 68% in the same conditions.
    Journal of Semiconductors 10/2011; 32(10):105010. DOI:10.1088/1674-4926/32/10/105010
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