Conference Proceeding

Co-design methodology to provide high ESD protection levels in the advanced RF circuits

IMEC, Leuven, Belgium
10/2003; pp.1 - 9 In proceeding of: Electrical Overstress/Electrostatic Discharge Symposium, 2003. EOS/ESD '03.
Source: IEEE Xplore

ABSTRACT This paper describes an approach to design ESD protection for integrated Low Noise Amplifier (LNA) circuits, used in narrowband transceiver front-ends. The RF constraints on the ESD devices are relaxed by co-designing the RF and the ESD blocks, considering them as one single circuit to optimize. The method is applied to the design of 0.25 mum CMOS LNA. Circuit protection levels higher than 3 kV HBM stress are achieved using conventional high capacitive ggNMOS snapback devices.

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Keywords

3 kV HBM stress
 
Circuit protection levels higher
 
design ESD protection
 
ESD devices
 
Low Noise Amplifier
 
narrowband transceiver front-ends
 
single circuit