Redundancy techniques, such as N -tuple modular redundancy (NMR), has been widely used to correct faulty behavior of components and achieve high reliability. Almost all redundancy-based strategies rely on a majority voting. The voter, therefore, becomes a critical unit for the correct operation of any NMR system. In this paper, we propose a voterless fault-tolerant strategy to implement a robust NMR system design. We show that using a novel fault-tolerant communication mechanism, namely logic code division multiple access, we can transfer data with extremely low error rates among N modules and completely eliminate the need for a centralized voter unit. Such a highly reliable strategy is vital for future nanosystems in which high defect rate is expected. Experimental results are also reported to verify the concept, clarify the design procedure, and measure the system's reliability.
[Show abstract][Hide abstract] ABSTRACT: High computing capabilities and limited number of input/output pins of modern integrated circuits require an efficient and reliable interconnection architecture. The proposed communication scheme allows a large number of IP cores to send data over a single wire using logic code division multiple access (LCDMA) technique. Reliability is increased using duplication with logic comparison (DLC) which enhances the error correction capability of the conventional LCDMA approach. Two implementations of the proposed LCDMA-DLC interconnection scheme, FPGA and ASIC, are considered. It is shown that LCDMA-DLC scheme reduces the hardware overhead and power consumption, with slightly better bit error rate (BER) performance, in comparison to the conventional triple modular redundancy (TMR) approach. MATLAB simulation results for LCDMA-DLC scheme with different spreading code lengths, at a constant SNR=10, show that BER improvement ranges from 5.8 times, for code length of 16 bits, up to 175 times, for code length of 32 bits in respect to 8-bit code length. In addition, the obtained results of ASIC implementation show that area and power overheads are approximately 3 times for LCDMA-TMR, and 2 times for LCDMA-DLC, in respect to the original LCDMA scheme, respectively.
[Show abstract][Hide abstract] ABSTRACT: High computing capabilities and limited number of input/output pins of modern integrated circuits require an efficient and reliable interconnection architecture. The proposed communication scheme allows a large number of IP cores to send data over a single wire using logic code division multiple access (LCDMA) technique. Reliability is increased by using hardware redundancy, and three LCDMA-based fault tolerant designs are proposed: (a) duplication with logic comparison (DLC), (b) conventional triple modular redundancy (TMR), and (c) triple modular redundancy with sign voter (TSV). With aim to detect a received bit from chip sequence, LCDMA-DLC and LCDMA-TSV designs compare absolute values of the sums, while LCDMA-TMR compares only sign bits of the sums generated at the outputs of decoders. All proposed designs are implemented in FPGA and ASIC technologies. MATLAB simulation results show that increasing the length of spreading codes affects to an increase in reliability. A comparative analysis of the proposed fault tolerant designs in terms of hardware complexity, latency, power consumption and error detecting and correcting capability is conducted. It is shown that LCDMA-DLC design has lower hardware overhead and power consumption, with satisfactory better bit error rate (BER) performance, in comparison to LCDMA-TMR and LCDMA-TSV approach.
"Modular redundancy techniques have been widely researched in the past few decades and include Triple modular redundancy (TMR) - and N-tuple modular redundancy . Designs of new voter circuits  and even NMR systems without a centralized voter  have been proposed. A more fine-grained built-in fault tolerance technique is the structural redundancy . "
[Show abstract][Hide abstract] ABSTRACT: High defect rates are associated with novel nanodevice-based systems owing to unconventional and self-assembly-based manufacturing processes. Furthermore, in emerging nanosystems, fault mechanisms and distributions may be very different from CMOS due to unique physical layer aspects, and emerging circuits and logic styles. Development of analytical fault models for nanosystems is necessary to explore the design of novel fault tolerance schemes that could be more effective than conventional schemes. In this paper, we first develop a detailed analytical fault model for the nanoscale application specific integrated circuits (NASIC) computing fabric and show that the probability of 0-to-1 faults is much higher than of 1-to-0 faults. We then show that in fabrics with unequal fault probabilities, using biased voting schemes, as opposed to conventional majority voting, could provide better yield. However, due to the high defect rates, voting will need to be combined with more fine-grained structural redundancy for acceptable yield. This entails degradation in performance (operating frequency) due to an increase in circuit fan-in and fan-out. We, therefore, introduce a new class of redundancy schemes called FastTrack that combine nonuniform structural redundancy with uniquely biased nanoscale voters to achieve greater yield without a commensurate loss in performance. A variety of such techniques are employed on a wire streaming processor (WISP-0) implemented on the NASIC fabric. We show that FastTrack schemes can provide 23% higher effective yield than conventional redundancy schemes even at 10% defect rates along with 79% lesser performance degradation.
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