A Fault-Tolerant Interconnect Mechanism for NMR Nanoarchitectures
ABSTRACT Redundancy techniques, such as N -tuple modular redundancy (NMR), has been widely used to correct faulty behavior of components and achieve high reliability. Almost all redundancy-based strategies rely on a majority voting. The voter, therefore, becomes a critical unit for the correct operation of any NMR system. In this paper, we propose a voterless fault-tolerant strategy to implement a robust NMR system design. We show that using a novel fault-tolerant communication mechanism, namely logic code division multiple access, we can transfer data with extremely low error rates among N modules and completely eliminate the need for a centralized voter unit. Such a highly reliable strategy is vital for future nanosystems in which high defect rate is expected. Experimental results are also reported to verify the concept, clarify the design procedure, and measure the system's reliability.
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ABSTRACT: High computing capabilities and limited number of input/output pins of modern integrated circuits require an efficient and reliable interconnection architecture. The proposed communication scheme allows a large number of IP cores to send data over a single wire using logic code division multiple access (LCDMA) technique. Reliability is increased using duplication with logic comparison (DLC) which enhances the error correction capability of the conventional LCDMA approach. Two implementations of the proposed LCDMA-DLC interconnection scheme, FPGA and ASIC, are considered. It is shown that LCDMA-DLC scheme reduces the hardware overhead and power consumption, with slightly better bit error rate (BER) performance, in comparison to the conventional triple modular redundancy (TMR) approach. MATLAB simulation results for LCDMA-DLC scheme with different spreading code lengths, at a constant SNR=10, show that BER improvement ranges from 5.8 times, for code length of 16 bits, up to 175 times, for code length of 32 bits in respect to 8-bit code length. In addition, the obtained results of ASIC implementation show that area and power overheads are approximately 3 times for LCDMA-TMR, and 2 times for LCDMA-DLC, in respect to the original LCDMA scheme, respectively.Microelectronics Reliability 12/2014; · 1.21 Impact Factor
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ABSTRACT: Conducted an analysis of fault tolerant LCDMA-based interconnect candidates.•Described structures for LCDMA–DLC, LCDMA–TMR and LCDMA–TSV schemes.•Inserted additional evaluations of both FPGA and ASIC implementations.•Discussed the benefits of using LCDMA–DLC architecture.•Concerned application of the LCDMA–DLC interconnection architecture.Microelectronics Reliability 10/2014; · 1.21 Impact Factor
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ABSTRACT: Due to the small size of nanoscale devices, they are highly prone to process disturbances which results in manufacturing defects. Some of the defects are randomly distributed throughout the nanodevice layer. Other disturbances tend to be local and lead to cluster defects caused by factors such as layer misintegration and line width variations. In this paper, we propose a method for identifying cluster defects from random ones. The motivation is to repair the cluster defects using rectangular ranges in a range matching content-addressable memory (RM-CAM) and random defects using triple-modular redundancy (TMR). It is believed a combination of these two approaches is more effective for repairing defects at high error rate with less resource. With the proposed fault repairing technique, defect recovery results are examined for different fault distribution scenarios. Also the mapping circuit structure required for two conceptual 32×32 and 64×64 bit RAMs are presented and their speed, power and transistor count are reported.Electrical Engineering (ICEE), 2013 21st Iranian Conference on; 01/2013