Article

A Fault-Tolerant Interconnect Mechanism for NMR Nanoarchitectures

Electr. Eng. Dept., Univ. of Texas at Dallas, Richardson, TX, USA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (Impact Factor: 1.14). 11/2010; 18(10):1433 - 1446. DOI: 10.1109/TVLSI.2009.2024779
Source: IEEE Xplore

ABSTRACT Redundancy techniques, such as N -tuple modular redundancy (NMR), has been widely used to correct faulty behavior of components and achieve high reliability. Almost all redundancy-based strategies rely on a majority voting. The voter, therefore, becomes a critical unit for the correct operation of any NMR system. In this paper, we propose a voterless fault-tolerant strategy to implement a robust NMR system design. We show that using a novel fault-tolerant communication mechanism, namely logic code division multiple access, we can transfer data with extremely low error rates among N modules and completely eliminate the need for a centralized voter unit. Such a highly reliable strategy is vital for future nanosystems in which high defect rate is expected. Experimental results are also reported to verify the concept, clarify the design procedure, and measure the system's reliability.

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    • "However, extended bandwidth allows data recovery. It improves the reliability in spite of a few spreading bits loss in the recovery process [14] "
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    ABSTRACT: High computing capabilities and limited number of input/output pins of modern integrated circuits require an efficient and reliable interconnection architecture. The proposed communication scheme allows a large number of IP cores to send data over a single wire using logic code division multiple access (LCDMA) technique. Reliability is increased by using hardware redundancy, and three LCDMA-based fault tolerant designs are proposed: (a) duplication with logic comparison (DLC), (b) conventional triple modular redundancy (TMR), and (c) triple modular redundancy with sign voter (TSV). With aim to detect a received bit from chip sequence, LCDMA-DLC and LCDMA-TSV designs compare absolute values of the sums, while LCDMA-TMR compares only sign bits of the sums generated at the outputs of decoders. All proposed designs are implemented in FPGA and ASIC technologies. MATLAB simulation results show that increasing the length of spreading codes affects to an increase in reliability. A comparative analysis of the proposed fault tolerant designs in terms of hardware complexity, latency, power consumption and error detecting and correcting capability is conducted. It is shown that LCDMA-DLC design has lower hardware overhead and power consumption, with satisfactory better bit error rate (BER) performance, in comparison to LCDMA-TMR and LCDMA-TSV approach.
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    • "Modular redundancy techniques have been widely researched in the past few decades and include Triple modular redundancy (TMR) [14]-[17] and N-tuple modular redundancy [18]. Designs of new voter circuits [19][20] and even NMR systems without a centralized voter [21] have been proposed. A more fine-grained built-in fault tolerance technique is the structural redundancy [22]. "
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