Three-Dimensional Real-Space Simulation of Surface Roughness in Silicon Nanowire FETs
ABSTRACT We address the transport properties of narrow gate-all-around silicon nanowires in the presence of surface-roughness (SR) scattering at the Si/SiO2 interface, considering nanowire transistors with a cross section of 3 times 3 nm2 and gate length of 15 nm. We present transfer characteristics and effective-mobility calculations based on a full 3-D real-space self-consistent Poisson-Schrodinger solver within the nonequilibrium Green's function formalism. The effect of SR is included via a geometrical method consisting in a random realization of potential fluctuations described via an exponential autocorrelation law. The influence on transfer characteristics and on low-field mobility is evaluated by comparison with the clean case and for different values of the root mean square of potential fluctuations. The method allows us to exactly account for mode-mixing and subband fluctuations and to evaluate the effect of SR up to all orders of the interaction. We find that SR scattering is mainly responsible for positive threshold-voltage shift in the low-field regime, whereas SR-limited mobility slowly depends on the linear charge density, showing the inefficiency of mode-mixing scattering mechanism for very narrow wires.
Conference Paper: Quantum simulation of self-heating effects in rough Si nanowire FETs[Show abstract] [Hide abstract]
ABSTRACT: We present a quantum approach to simulate self-heating effects in transistors based on silicon nanowires and estimate the resulting performance degradation. Our self-consistent thermoelectric simulations are based on the nonequilibrium Green's function approach and provide the heat power transferred from electrons to phonons, thus allowing the calculation of the local temperature and its impact on the transistor output characteristics. We apply our approach to the simulation of a tri-gate transistor with a 14 nm channel length in the presence of surface roughness. Our results clearly indicate that self-heating effects are enhanced by surface roughness, with important consequences on the on-current of the device.2014 International Workshop on Computational Electronics (IWCE); 06/2014
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ABSTRACT: A comprehensive study is conducted on the electron transport in conductive polymer matrix composites (CPMCs), employing the nonequilibrium Green’s function formalism. This paper provides a microscopic insight into the electron tunneling through the potential barriers existing between conducting sites. It is shown that Wentzel–Kramers–Brillouin approximation as well as other models with simple barrier shapes, which are widely used in literature, can lead to inaccurate results in comparison with the quantum mechanical approach using a hyperbolic barrier. In this paper, unlike most previous ones, percolation-related effects are disregarded for further focus on electron transport through the polymer potential barriers. It is assumed that a tunneling-conductive channel exists between the electrodes. This can be created either by applying electric field alignment or using a filler volume fraction higher than the percolation threshold. A two electrode resistive device is studied and the results indicate that a conductor–insulator transition occurs at a barrier thickness of $sim 1.7$ nm and the barrier thickness should be larger than several angstroms. Next, a novel tunneling field-effect structure based on CPMCs is introduced and its characteristics are comprehensively investigated. This device features a remarkably simple structure, an extremely high channel to gate coupling, a large transconductance, and a high current level. Besides, it has the advantage of being based on polymers. This ensures favorable physical properties, ease of fabrication, and low-cost processing techniques.IEEE Transactions on Electron Devices 05/2015; 62(5):1584-1589. DOI:10.1109/TED.2015.2411992 · 2.36 Impact Factor
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ABSTRACT: We present a numerical study based on a full quantum transport model to investigate the effects of interface traps in nanowire InAs Tunnel-FETs and MOSFETs by varying the trap energy level, its position and the working temperature. Our 3-D self-consistent simulations show that in Tunnel-FETs even a single trap can deteriorate the inverse subthreshold slope of a nanowire InAs Tunnel-FET; shallow traps have the largest impact on subthreshold slope; and the inelastic phonon-assisted tunneling through interface traps results in a temperature dependence of the Tunnel-FET characteristics. The impact of traps on the IV characteristics of MOSFETs is instead less dramatic, and the traps induced degradation of the subthreshold swing can be effectively contrasted by an aggressive oxide thickness scaling. Finally, we present a comparative analysis of the impact of interface traps on the performance variability of nanowire InAs Tunnel-FETs and MOSFETs by considering random distributions of traps.ECS Transactions 05/2014; 61(2):237-251. DOI:10.1149/06102.0237ecst