Article

Three-Dimensional Real-Space Simulation of Surface Roughness in Silicon Nanowire FETs

IMEP-LAHC, Grenoble INP MINATEC, Grenoble, France
IEEE Transactions on Electron Devices (Impact Factor: 2.36). 11/2009; 56(10):2186 - 2192. DOI: 10.1109/TED.2009.2028382
Source: IEEE Xplore

ABSTRACT We address the transport properties of narrow gate-all-around silicon nanowires in the presence of surface-roughness (SR) scattering at the Si/SiO2 interface, considering nanowire transistors with a cross section of 3 times 3 nm2 and gate length of 15 nm. We present transfer characteristics and effective-mobility calculations based on a full 3-D real-space self-consistent Poisson-Schrodinger solver within the nonequilibrium Green's function formalism. The effect of SR is included via a geometrical method consisting in a random realization of potential fluctuations described via an exponential autocorrelation law. The influence on transfer characteristics and on low-field mobility is evaluated by comparison with the clean case and for different values of the root mean square of potential fluctuations. The method allows us to exactly account for mode-mixing and subband fluctuations and to evaluate the effect of SR up to all orders of the interaction. We find that SR scattering is mainly responsible for positive threshold-voltage shift in the low-field regime, whereas SR-limited mobility slowly depends on the linear charge density, showing the inefficiency of mode-mixing scattering mechanism for very narrow wires.

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