Three-Dimensional Real-Space Simulation of Surface Roughness in Silicon Nanowire FETs
ABSTRACT We address the transport properties of narrow gate-all-around silicon nanowires in the presence of surface-roughness (SR) scattering at the Si/SiO2 interface, considering nanowire transistors with a cross section of 3 times 3 nm2 and gate length of 15 nm. We present transfer characteristics and effective-mobility calculations based on a full 3-D real-space self-consistent Poisson-Schrodinger solver within the nonequilibrium Green's function formalism. The effect of SR is included via a geometrical method consisting in a random realization of potential fluctuations described via an exponential autocorrelation law. The influence on transfer characteristics and on low-field mobility is evaluated by comparison with the clean case and for different values of the root mean square of potential fluctuations. The method allows us to exactly account for mode-mixing and subband fluctuations and to evaluate the effect of SR up to all orders of the interaction. We find that SR scattering is mainly responsible for positive threshold-voltage shift in the low-field regime, whereas SR-limited mobility slowly depends on the linear charge density, showing the inefficiency of mode-mixing scattering mechanism for very narrow wires.
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ABSTRACT: Strained Si and SiGe tri-gate nanowire (NW) MOSFETs with significantly reduced line-edge roughness and smooth sidewalls were fabricated by a novel anisotropic thermal etching technique in H<sub>2</sub> atmosphere. Effective carrier mobility measurements revealed mobility enhancements for the strained-Si NW n-MOSFETs and the strained-SiGe NW p-MOSFETs by factors of 1.9 and 1.6 against unstrained Si NW n- and p-MOSFETs, respectively. It was also shown that the sidewall shapes of the NWs have a great impact on the mobility via the difference in the surface roughness scattering on the sidewalls.Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
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ABSTRACT: For the first time, we have successfully fabricated gate-all-around twin silicon nanowire transistor (TSNWFET) on bulk Si wafer using self-aligned damascene-gate process. With 10nm diameter nanowire, saturation currents through twin nanowires of 2.64 mA/mum, 1.11 mA/mum for n-channel TSNWFET and p-channel TSNWFET are obtained, respectively. No roll-off of threshold voltages, ~70 mV/dec. of substhreshold swing (SS), and ~20 mV/V of drain induced barrier lowering(DIBL) down to 30 nm gate length are observed for both n-ch and p-ch TSNWFETsElectron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
Chapter: Transport in Nanostructures[show abstract] [hide abstract]
ABSTRACT: Transport in Nanostructures reviews the results of experimental research into mesoscopic devices, and develops a detailed theoretical framework for understanding their behavior. The authors discuss the key observable phenomena in nanostructures, including phase interference and weak localization. They then describe quantum confined systems, transmission in nanostructures, quantum dots and single electron phenomena. Separate chapters cover interference in diffusive transport and temperature decay of fluctuations, and a chapter on nonequilibrium transport and nanodevices concludes the book. Throughout, Ferry and Goodnick interweave experimental results with the appropriate theoretical formalism. Profusely illustrated, the book will be of great interest to graduate students taking courses in mesoscopic physics or nanoelectronics, as well as to researchers working on semiconductor nanostructures or the development of new ultrasmall devices.12/2007: pages 115-169;