Conference Paper

32-Mb 2T1R SPRAM with localized bi-directional write driver and ‘1’/‘0’ dual-array equalized reference cell

Conference: VLSI Circuits, 2009 Symposium on
Source: IEEE Xplore

ABSTRACT A 32-Mb SPin-transfer torque RAM (SPRAM) chip was demonstrated with an access time of 32 ns and a cell write-time of 40 ns at a supply voltage of 1.8 V. The chip was fabricated with 150-nm CMOS and a 100 × 200 nm tunnel magnetoresistive device element. This chip features three circuit technologies suitable for a large-scale array: 1) a two-transistor, one-resistor (2T1R) type memory cell for achieving a sufficiently large writing current despite the small cell size, 2) a compact read/write separated hierarchy bit/source-line structure with a localized bi-directional write driver for efficiently distributing writing current, and 3) a ‘1’/‘0’ dual-array equalized reference cell for stable read operation.

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