Conference Proceeding

A novel LV LP CMOS internal topology of CCII+ and its application in current-mode integrated circuits

Electr. & Inf. Eng. Dept., Univ. of L'Aquila, L'Aquila, Italy
08/2009; DOI:10.1109/RME.2009.5201310 In proceeding of: Research in Microelectronics and Electronics, 2009. PRIME 2009. Ph.D.
Source: IEEE Xplore

ABSTRACT In this paper we present a novel internal architecture of low-voltage and low-power positive second-generation current conveyor (CCII+). The proposed internal circuit topology, designed in standard CMOS technology (AMS 0.35 ¿m), employs an n-type differential pair as input stage, while a cascoded push-pull configuration implements a very high impedance output stage. A degenerated nMOS common drain topology reduces X node impedance. The choice of internal CCII+ architecture, concerning both its stage architecture and transistor sizes, has been made in the direction of designing a quasi-ideal CCII+ in terms of parasitic components at its terminals. The developed CCII+ operates at low supply voltages of ±1 V with a total power consumption of about 300 ¿W, so it is suitable for general purpose portable applications. It has been also characterized implementing well-known applications, both in time and frequency domains, such as signal processing circuits and impedance simulators.

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    IEEE Sensors Journal 04/2013; Early Access Articles. · 1.52 Impact Factor
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Keywords

CCII+
 
degenerated nMOS common
 
developed CCII+
 
frequency domains
 
general purpose portable applications
 
impedance simulators
 
input stage
 
internal CCII+ architecture
 
low-power positive second-generation current conveyor
 
novel internal architecture
 
parasitic components
 
proposed internal circuit topology
 
quasi-ideal CCII+
 
signal processing circuits
 
standard CMOS technology
 
well-known applications
 
X node impedance