High velocity Si-nanodot : A candidate for SRAM applications at 16nm node and below
ABSTRACT We report a new nanodot MOSFET, based on the use of Bulk wafer and Silicon-On-Nothing technology, requiring neither CMP nor extra photo-lithographic step. SRAM-application oriented nanodot devices were fabricated using this new process. Record performance among the nanometric gate-all-around MOSFET state-of-the-art is obtained thanks to a high quality transport.
[Show abstract] [Hide abstract]
ABSTRACT: In this work, we propose a novel transistor called dual-channel source/drain-tied (DCSDT) MOSFET. The process for producing the device employs the multiple epitaxial growths of SiGe/Si layers and selective SiGe removal to form the block oxide island (BOI) in this work. Due to the source/drain-tied scheme giving more pass way to dissipate generated heat, the both DC and RF/analog performance of the device are not seriously affected according to the numerical simulation results.Integrated Ferroelectrics 01/2011; 129(1):74-79. DOI:10.1080/10584587.2011.576913 · 0.37 Impact Factor
[Show abstract] [Hide abstract]
ABSTRACT: Gate semi-around silicon nanowire (SiNW) FETs have been fabricated and their electrical characteristics, especially on the drivability, have been assessed for future high performance devices. Among different wire size, a SiNW FET with a cross-section of 12 × 19 nm<sup>2</sup> has shown an improvement in the on-current (I<sub>ON</sub>) when normalized by the channel peripheral length. A high I<sub>ON</sub> over 1600 μA/μm at an overdrive voltage of 1 V has been achieved with a gate length and an oxide thickness of 65 and 3 nm, respectively. The origin of the high drivability has been speculated by higher carrier density, improved carrier mobility and the reduction in the series resistance.Solid-State Device Research Conference (ESSDERC), 2010 Proceedings of the European; 10/2010
Conference Paper: Materials and structures for future nano CMOS[Show abstract] [Hide abstract]
ABSTRACT: Recently, CMOS downsizing has been accelerated very aggressively in both production and research levels, and even beautiful transistor operation of several nm gate length CMOS devices were reported in conferences. However, many serious problems are expected for implementing small-geometry MOSFETs into large scale integrated circuits. It is still questionable if we can successfully introduce deep sub-10 nm CMOS LSIs into market, because the problems expected at this moment - such as Ion/Ioff ratio, current drive, variation in the electrical characteristics, concerns for the yield, reliability and manufacturing cost. Considering the above situation, we have conducted nano-CMOS studies in advance to provide possible solutions to the future expected problems. The conclusion obtained by the study was that, in the nano-CMOS era, aggressive introduction of new materials, processes, structures, and operation concepts is required to solve the problems. Especially, the thinning of the gate oxide is the bottleneck of the future down-scaling, and thus, new materials and process technologies which enable decrease in the EOT (Equivalent Oxide Thickness) value less than 0.5 nm are very important. Also, changing the material of source/drain from semiconductor to metal is necessary to suppression of the diffusion of the dopant and thus, to secure the effective channel length less than several nm. Multigate structure such as Fin, Tri-gate, or nanowire is inevitable to suppress the short-channel effect. Unfortunately, there are no candidates among the so-called 'beyond CMOS' or 'Post Si' new devices, which are believed to really replace CMOS transistors usable for the products of highly integrated circuits within 20 years. Thus, our opinion is that we need to still continue CMOS based transistors with 'More Moore' approach with combining that of 'More than Moore'. Good news is that Si Nanowire FETs have been found to have very promising characteristics with - igh Ion/Ioff ratio and high drive current. In this invited talk at NMDC 2011, future of nano-CMOS technology is presented. However, in this proceedings, only the part of new structure for future nano-CMOS, specifically that of Si-nanowire FETs is described because the limit of the number of pages.Nanotechnology Materials and Devices Conference (NMDC), 2011 IEEE; 01/2011