IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 2, FEBRUARY 2010 519
Start-Up and Dynamic Modeling of the Multilevel
Modular Capacitor-Clamped Converter
Faisal H. Khan, Member, IEEE, Leon M. Tolbert, Senior Member, IEEE, and William E. Webb
the capacitors of the MMCCC explains the start-up and steady-
state voltage balancing. Once these capacitor voltages are found
for different time intervals, the start-up and steady-state voltages
at various nodes of the MMCCC can be obtained. This analysis
provides the necessary proof that explains the stable operation of
circuit. In addition, the analysis also shows how the LV side of the
ratio of the circuit is N. In addition to the analytical and simulation
results, experimental results are included to support the analytical
proof of concept.
Index Terms—DC–DC power conversion, power capacitors,
power conversion, power electronics, power semiconductor
can be designed to operate at very high efficiency. The mul-
tilevel modular capacitor-clamped dc–dc converter (MMCCC)
presented in  had a capacitor-clamped modular architecture
or charge-pump technology –. The MMCCC topology
has a bidirectional power management feature, and multiple
loads and sources can be simultaneously connected to this con-
verter. MMCCC’s various features and applications in hybrid
electric and fuel cell automobiles were demonstrated in 
and . The originality and proof of concept of this topol-
ogy was verified by several simulation and experimental results
in these literatures. As the MMCCC topology is a capacitor-
clamped circuit, the proper operation and the capability to pro-
duce a certain conversion ratio (CR) can be proven by knowing
the various capacitor voltages during the start-up and steady-
state operation of the converter.
APACITOR-clamped or switched-capacitor converters
are based on capacitive energy transfer mechanisms, and
by Oak Ridge National Laboratory under UT-Battelle Contract 4000007596.
Recommended for publication by Associate Editor A. Rufer.
versity of Utah, Salt Lake City, UT 84112 USA (e-mail: email@example.com).
W. E. Webb is with the Electric Power Research Institute (EPRI), Knoxville,
TN 37932 USA (e-mail: firstname.lastname@example.org).
L. M. Tolbert is with the Department of Electrical and Computer Engi-
neering, University of Tennessee, Knoxville, TN 37996-2100 USA, and also
with Oak Ridge National Laboratory, Oak Ridge, TN 37831 USA (e-mail:
Color versions of one or more of the figures in this paper are available online
Digital Object Identifier 10.1109/TPEL.2009.2025273
The MMCCC is inherently a bidirectional dc–dc converter.
side experiences a voltage of VLV. On the other hand, a voltage
source VLVconnected at the LV side produces a load voltage of
VHVat the HV side. In both cases, VHV/VLV= N, where N is
the CR of the circuit. The schematic of a five-level MMCCC is
shown in Fig. 1.
This paper will provide the analytical derivation of the MM-
CCC voltage transfer mechanisms. The mathematical expres-
sions rely on the MMCCC circuit’s inherent nature to produce
a specific CR. In addition, several simulation and experimental
voltage expressions derived in this paper.
II. BASIC CONSTRUCTION AND OPERATION OF THE MMCCC
The basic operation of the MMCCC has some similarities
with the flying capacitor multilevel dc–dc converter (FCMDC)
shown in –. It was presented in  that the MMCCC
exhibits some of the favorable properties of the FCMDC and
the series–parallel converter , . The property that achieves
equal voltage stress across the transistors was adopted from the
FCMDC topology, and the modular construction was adopted
is a five-level MMCCC, and the circuit has a CR equal to 5. The
terminology of voltage levels present in the circuit has been
used slightly differently in this paper. Usually, a multilevel dc–
dc converter with a CR equal to N is defined as an (N + 1)-
level converter. This convention was adopted from multilevel
inverters where zero voltage is a working voltage level in the
level for the MMCCC in this paper.
An N-level MMCCC circuit requires (3N − 2) transistors,
and the method of charge transfer requires two subintervals
 shown in Fig. 2. Compared to the FCMDC topology, the
requirement of only two subintervals, regardless of the CR of
Eachtransistorwillbe ONinoneofthetwosubintervalsand OFF
in the other, which means that the transistors can be separated
into two groups that have complementary operations. In the
MMCCC shown in Fig. 1, transistors SR1–SR7 are activated in
subinterval 1 and SB1–SB6 are activated in subinterval 2.
For ease of understanding, the working principle of the MM-
CCC is discussed in the down conversion or buck mode in
this paper. In a five-level FCMDC, it takes five subintervals
to complete the power transfer operation from the input to
the output of the circuit. However, in the MMCCC, multiple
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520IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 2, FEBRUARY 2010
Fig. 1.Schematic of a five-level MMCCC circuit with four modules.
(a) Schematic of state 1 or the first subinterval. (b) Schematic of state 2 or
the second subinterval.
Steady-state operational diagrams of a five-level MMCCC.
mutually exclusive charge–discharge operations are executed in
only two subintervals. In the first subinterval, C5 and C1 are
being charged from VHV, and C4is discharged through C3and
tions are executed simultaneously. Inthe second subinterval,C5
is discharged to C4and C1, and C3is discharged to C2and C1.
the next subinterval. Although, it seems that C1is always being
expression shows otherwise. It will be shown later how in each
subinterval, C1is being charged for some time, and discharged
for the remaining time in the subinterval. The charge–discharge
mechanism of various capacitors inside the MMCCC is shown
in Table I. In this table, the charge–discharge operation of the
MMCCC is also compared with a five-level FCMDC. The de-
tailed operating principle of the MMCCC can be found in 
CHARGE–DISCHARGE OPERATION IN VARIOUS SUBINTERVALS OF AN FCMDC
AND MMCCC CONVERTER
The MMCCC circuit uses a hybrid architecture that com-
bines the favorable features of series–parallel converter and
FCMDC converter . The modeling technique of various
published literatures , , , , –. The MMCCC
modeling technique discussed in the following sections was not
adopted from any particular previous derivation; rather, it was
influenced by the previous works. The MMCCC circuit has two
modes of operations: dynamic state or start-up and the steady
state. Two different sets of boundary conditions are applied to
deduce the equivalent models of the operational circuit in these
two modes. Section III explains how the various capacitors at-
tain steady voltages once the converter is energized. Section IV
discusses the voltage variations of the capacitors once a load is
connected to the converter.
III. START-UP ANALYSIS OF MMCCC
The MMCCC produces a CR based on the stored and trans-
ferred charges among the capacitors. It is required to find the
capacitor voltages at different time intervals to prove the con-
cept of the MMCCC topology. The following assumptions were
made prior to the actual computational steps: 1) capacitors do
voltage stress across the transistors and makes the analysis in
the most conservative manner, and 2) RC ? T/2, where R is the
KHAN et al.: START-UP AND DYNAMIC MODELING OF THE MULTILEVEL MODULAR CAPACITOR-CLAMPED CONVERTER 521
Fig. 3. Start-up arrangement of a five-level MMCCC circuit.
series path resistance of a capacitor charging circuit, C is the
capacitance, and T is one switching period.
During start-up, it is also assumed that the converter is work-
ing in up-conversion (boost) mode, and the circuit is operating
without any load. Once the capacitors obtain the proper operat-
ing voltages, the converter starts operating in the steady state,
are variations in the capacitor voltages in both sub-intervals of
the converter . These variations will depend on the load cur-
rent, operating frequency, and capacitor sizing. The second part
of the analysis works with the steady state capacitor voltages
during the two sub-intervals of the converter.
Using its bi-directional power handling capability, the MM-
CCC can seamlessly work in buck, boost or dual-source mode.
To ensure a proper charge balancing during start-up, a voltage
source of VLVis connected to the LV side of the converter, and
the HV side is left open during the start-up phase. To avoid
undesirable voltage stress across the transistors, the HV side is
not connected during the first 100 cycles of the start-up state.
It will be shown later how the capacitors attain the normal volt-
ages across them within the first 100 cycles of operation. The
transistors are operated in sequential steps with the use of a mi-
crocontroller. Fig. 3 shows the schematic of the MMCCC with
the required arrangement for start-up operation, and Table II
shows the required transistor operation for the start-up steps.
Step 3 and step 4 in Table II are repeated 100 times to ensure
appropriate voltage build up across the capacitors. If the circuit
works without any loss or voltage drop across any active or pas-
5. At steady state, the capacitors should have voltages like the
following to ensure equal voltage stresses across the transistors:
VC2= VLV,VC3= 2VLV,
Thus, if the capacitor voltages are found in this form at the
end of the modeling, it indicates that the MMCCC circuit can
produce the expected CR.
ACTIVE TRANSISTORS AND CAPACITORS IN THE START-UP STEPS
A. Step 1 of the Start-Up Process
The operation of this step is shown in Fig. 4(a). In this step,
capacitors C1and C2are connected to the VLV source. Thus,
the voltage equations of the capacitors would be
VC1(t1) = VC2(t1) = VLV
VC3(t1) = VC4(t1) = VC5(t1) = 0.
B. Step 2 of the Start-Up Process
This step involves the discharging operation of C2and the
charging operation of C3. The operation is shown in Fig. 4(b).
VC1(t2) = VLV
VC2(t2) = VC2(t1) + [VLV+ VC2(t1) − VC3(t1)]
= 0.5[VC2(t1) + VC3(t1) + VLV]
VC3(t2) = VC3(t1) + [VLV+ VC2(t1) − VC3(t1)]
= 0.5[VC2(t1) + VC3(t1) + VLV]
VC4(t2) = VC5(t2) = 0.
522 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 2, FEBRUARY 2010
(a) Step 1. (b) Step 2. (c) Step 3. (d) Step 4.
C. Step 3 of the Start-Up Process
The operational diagram of this step is shown in Fig. 4(c). In
this step, the charge is transferred from C3to C4. C2is again
connected to VLVas in step 1. Thus, the voltage equations are
VC1(t3) = VC2(t3) = VLV
VC3(t3) = 0.5[VC3(t2) + VC4(t2) − VLV]
VC4(t2) = 0.5[VC3(t2) + VC4(t2) + VLV]
VC5(t3) = VC5(t2) = 0.
D. Step 4 of the Start-Up Process
This step involves the operations that took place in step 2
with an additional charge transfer action from C4to C5. The
operational diagram of step 4 is shown in Fig. 4(d), and the
voltage equations are given as
VC1(t4) = VLV
VC2(t4) = 0.5[VC2(t3) + VC3(t3)] − 0.5VLV
VC3(t4) = 0.5[VC2(t3) + VC3(t3)] + 0.5VLV
VC4(t4) = 0.5[VC4(t3) + VC5(t3)] − 0.5VLV
VC5(t4) = 0.5[VC4(t3) + VC5(t3)] + 0.5VLV.
Using (1)–(4), the capacitor voltages at the end of step 2 are
The values found from (16) will be used as the initial condi-
tions for step 3, and the voltages at the end of step 3 will be used
as the initial voltages for step 4. From the operating principle of
the converter, all odd indexed steps become equivalent once the
circuit completes the first four steps. This is also true of all even
indexed steps. Thus, the circuit is modeled using two repetitive
operations described in step 3 and 4. A variable k is defined
where k starts from 2. Therefore, the capacitor voltages in any
odd and even indexed steps can be generalized using (7)–(10)
and (11)–(15), and can be expressed in the following matrix,
shown in (17) and (18) at the bottom of this page.
Here, (17) and (18) are in the form y = Mx + b and z =
Ny + d. After doing the matrix manipulation and expressing
the constant factors in terms of VC1, shown in (19) and (20) at
the bottom of the next page, where
VC1(k) = VC1(k + 1) = VC1(k + n) = VLV.
VC1(k + 1)
VC2(k + 1)
VC3(k + 1)
VC4(k + 1)
VC5(k + 1)
VC1(k + 2)
VC2(k + 2)
VC3(k + 2)
VC4(k + 2)
VC5(k + 2)
VC1(k + 1)
VC2(k + 1)
VC3(k + 1)
VC4(k + 1)
VC5(k + 1)
KHAN et al.: START-UP AND DYNAMIC MODELING OF THE MULTILEVEL MODULAR CAPACITOR-CLAMPED CONVERTER 523
After n iterations, the final capacitor voltage vector can be
f = (CA)nX0
where X0is the capacitor voltage matrix at the end of step 2
found in (16). Using MATLAB
and the final capacitor voltage matrix f can be calculated using
(21a) and (21b). Thus,
The start-up gating sequence is operated at a speed of
10000 steps/s, which is equal to the switching frequency
(10 kHz) of the converter at steady state. Thus, after 100 it-
erations or 10 ms
The analytical derivation presented in this section explains
the start-up operation of a five-level MMCCC circuit. In Fig. 2,
the two subintervals of the circuit in steady state are shown.
In the first subinterval, C5and C1are connected in series and
is another current path composed of C4,C3, and C1. In Fig. 2,
during state 1, C4is connected across the series combination
of C3and C1. Equation (23) shows that the voltage across C4
(3 VLV) is equal to the summation of voltages across C1(1 VLV)
and C3(2 VLV). Moreover, C2is connected across C1, and their
where n = 100
n = 40, all voltages have reached steady state for all practical purposes. Voltage
magnitudes are normalized to VLV. Each iteration takes 100 µs.
Analytically derived capacitor voltage variations with iterations. At
voltages are also matched. Therefore, the voltages across the
capacitors during state 1 are matched to each other.
In state 2, C5is connected across the series circuit of C4and
C1. These voltages are also matched and can be seen in (23). In
C1, and the voltage across C3(2 VLV) is the same as the total
voltage across C1and C2(VLV+ VLV= 2VLV). Therefore, the
at either side, the load current will discharge the capacitors, and
charge transfer willtake place either from a voltage source (VLV
or VHV) to a capacitor or from one capacitor to another. In this
case, the steady-state capacitor voltages will be different from
the values stated in (23), and the analysis is shown in the next
The values of different capacitor voltages in (21a) were plot-
ted for different values of n varying in the range of 1 to 100,
as shown in Fig. 5. Two charge transfer operations in odd and
even indexed steps [shown in (19) and (20)] take place in one
clock cycle (for one value of n), and Fig. 5 shows the capacitor
voltages attheendoftheeven indexed step(second subinterval)
the capacitor voltages reach steady state after 40 iterations. To
verify the start-up operation using the technique presented in
VC1(k + 1)
VC2(k + 1)
VC3(k + 1)
VC4(k + 1)
VC5(k + 1)
VC1(k + 1)
VC2(k + 1)
VC3(k + 1)
VC4(k + 1)
VC5(k + 1)
VC1(k + 2)
VC2(k + 2)
VC3(k + 2)
VC4(k + 2)
VC5(k + 2)
VC1(k + 1)
VC2(k + 1)
VC3(k + 1)
VC4(k + 1)
VC5(k + 1)
524 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 2, FEBRUARY 2010
the start up period.
Experimental results of the capacitor voltages in the MMCCC during
this paper, a five-level MMCCC prototype has been constructed
on a printed circuit board. The circuit was designed for a max-
imum VHVof 220 V. For a five-level design, four modules are
used with each module having its own gate drive stages. Inside
one module, two bootstrap gate drive circuits (IR2110) have
been used to drive three IXFR120N20 MOSFETs. These MOS-
FETs have an ON resistance of 0.017 Ω at 25◦C, and are rated at
200 V, 105 A. General-purpose 4500-µF (3 × 1500 µF) 200-V
electrolytic capacitors having an equivalent series resistance
(ESR) of 0.04 Ω have been used. An LDS-Nicolet Vision XP
multichannel data acquisition system and a Lecroy Waverunner
high sampling digital oscilloscope were used to record the ca-
pacitor voltages VC1, VC2, VC3, VC4, and VC5, which are shown
in Fig. 6.
While comparing Figs. 5 and 6, the capacitor voltages were
normalized to 1 VLVin Fig. 5, and a 12.63-V source was used
as VLV in the experiment. The voltage across C5 reaches to
50.08 V after 0.06 s in the experiment; however, theoretically,
it should reach to 50.52 V (4 VLV) within 0.01 s. Because many
of the nonideal quantities such as drain-source resistance RDS
of the MOSFETs, capacitor ESR, and switching losses were not
included in the model, the time required to establish the proper
capacitor voltages was longer than the analytically computed
values. However, the experimental capacitor voltages were very
close to the analytically computed values. The comparison be-
percentage of error are summarized in Table III.
IV. STEADY-STATE ANALYSIS OF MMCCC
Section III presents the step-by-step start-up switching
scheme that can ensure safe operating voltage of the transis-
tors in the circuit. After 100 cycles, the capacitor voltages reach
the values shown in (23). During this time, the load was not
connected at the output, and the source VLVwas connected at
the LV side to balance the capacitor voltages. Therefore, the
values found from (23) will be used as the initial conditions
of the steady-state operation of the circuit. During steady-state
COMPARISON BETWEEN THE ANALYTICAL AND EXPERIMENTAL START-UP
VOLTAGES ACROSS THE CAPACITORS IN THE MMCCC
Fig. 7. Transition state timing diagram of a five-level MMCCC.
operation, the MMCCC circuit operates in the two states shown
in Fig. 2(a) and (b). Based on these operating states, the opera-
tion of the MMCCC circuit can be divided into four operating
zones. They are: 1) state 1; 2) transition 1 (from state 1 to state
2); 3) state 2; and 4) transition 2 (from state 2 to state 1). These
has a stable operating condition, voltage and current equations
at t4and t5would be the same as t0and t1, respectively, after
one clock cycle.
In a five-level converter, there are three current paths in state
1 (VE–C5–C1, C4–C3–C1, and C2–C1), and two current paths
in state 2 (C5–C4–C1and C3–C2–C1), as shown in Fig. 8. The
amount of ripple present at node 1 or at the output depends
on how much the capacitors are discharged, and the discharge
amount depends on how long the capacitors are connected to
the load. Therefore, to keep the ripple component equal in these
two subintervals or states, the duration of state 1 is 1.5 times the
duration of state 2 considering the increased number of current
paths present during state 1. Thus, for a five-level conversion,
(t2–t1) is 1.5 times (t4–t3). As a result, (t2–t1) = 0.6T and
(t4–t3) = 0.4T, where T is the time period of one cycle. The
reason for choosing these time intervals has been explained
in . For the proposed design, T is 100 µs for an operating
frequency of 10 kHz.
V. ANALYTICAL MODELING
A. Current and Voltage Equations in State 1
At time t = t1, the MMCCC circuit is on the verge of state
1, as shown in Fig. 7. Four constant offsets δ1,δ3,δ4, and δ5
are added to the capacitor voltages estimated at the begin-
ning of state 1 to include the effect of load current. Using the
KHAN et al.: START-UP AND DYNAMIC MODELING OF THE MULTILEVEL MODULAR CAPACITOR-CLAMPED CONVERTER 525
(a) State 1. (b) State 2.
Redefined steady-state diagrams with load connected at the LV side.
voltages found from the start-up analysis and considering sev-
eral constant deviations during steady state
VC5(t1) = 0.8E + δ5
VC4(t1) = 0.6E + δ4
VC3(t1) = 0.4E + δ3
VC2(t1) = VC1(t1) = 0.2E + δ1
where, E is the voltage amplitude of the source VE shown in
Fig. 8(a), and the following equations can be used as boundary
conditions derived from this figure. These boundary conditions
are not global, and are valid during state 1 only. Therefore
E = VC5+ VC1
thus, δ5+ δ1= 0 from (24) and (27)
VC4= VC3+ VC2
thus, δ4+ δ3+ δ1from (25)–(27)
I1+ I2+ I4+ I5= IL
from Fig. 8(a).
Depending on the direction of current and the capacitor volt-
ages, the following equations could be written at the end of state
1 (at t = t2):
VC5= 0.8E + δ5+I50.6T
VC4= 0.6E + δ4−I40.6T
VC3= 0.4E + δ3+I40.6T
VC1= VC2= 0.2E + δ1−I10.6T
Fig. 9.Schematic diagram of transition 1 operation.
where C1= C2= C3= C4= C5= C, and I3= I4and I1=
I2. Here, I1,I4, and I5 are the average currents during this
To satisfy the boundary condition (28), and using (31) and
I5= I1(as δ5+ δ1= 0).
In the same way, using the boundary condition (29), and
values from (32) and (34)
I1= 2I4as δ4= δ3+ δ1.
I1= I2= I5=2IL
and using (35),
VC5(t2) = 0.8E + δ5+6∆
VC4(t2) = 0.6E + δ4−3∆
VC3(t2) = 0.4E + δ3−3∆
VC1(t2) = VC2= 0.2E + δ1−6∆
where ∆ = ILT/C.
Now, there will be a transition from state 1 to state 2 at
t = t2, and it will continue until t = t3. This transition is shown
in Fig. 9. After this transition, the converter will be transformed
from the circuit shown in Fig. 8(a) to that shown in Fig. 8(b).
Therefore, the capacitor voltages found at the end of state 1 will
be the inputs in transition 1, and the voltages found at the end
of transition 1 will be used as the inputs in state 2.
B. Current and Voltage Equations in Transition 1
During the transition process, all five capacitors participate
in the charge transfer process simultaneously. However, for the
convenience of the analysis, it is assumed that this operation
takes place in several steps. These steps are such that the effect
526 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 2, FEBRUARY 2010
of interconnecting multiple capacitors simultaneously would
be the same as connecting them sequentially. Fig. 9 explains
the sequential capacitor switching in a transition state. This
transition is analyzed with the help of two switches S1 and
S2. It is assumed that S1 is turned on first, and then S2. For
the convenience of the analysis, the capacitor voltage at the
beginning of this transition state are defined as VC1, VC2, VC3,
VC4, and VC5rather than using the exact values found in (38)–
(41). Two intermediate variables VS1and VS2are defined such
VS1= VC5− (VC4+ VC1)
VS2= VC3− (VC2+ VC1).
When S1is closed and S2is open, C5will be discharged, and
will transfer some of its charge to C4and C1. Thus, there will
be a voltage drop across C5, and the change in VC5is
d(VC5) = VS1
where C5eq is the capacitance connected at terminal 5 in
Fig. 9 or the capacitance seen by C5. Thus, d(VC5) =
VS1(0.5C/(0.5C + C)) = VS1/3.
Due to this operation, the change in the voltage at node 4 is
d(V4) = VS1
d(V4)(C1/C1+ C4) =
In the same way, d(VC1) = VS1/3.
Thus, the new capacitor voltages are
C4= d(VC4) =
C5= VC5− d(VC5) = VC5−VS1
C4= VC4− d(VC4) = VC4−VS1
C1= VC1− d(VC1) = VC1−VS1
When S2is turned on, there occurs some charge transfer among
the capacitors, and as a result, the voltages of the capacitors
change. Using the same method as described previously
VC1(t3) = 0.2E +3∆
In the same way
VC2(t3) = 0.2E −9∆
VC3(t3) = 0.4E −3∆
VC4(t3) = 0.6E +3∆
VC5(t3) = 0.8E +9∆
Using the same method followed in state 1 and transition 1,
the capacitor voltages at the end of transition 2 can be obtained,
and they are summarized as follows:
VC1(t5) = VC2(t5) = 0.2E +
VC3(t5) = 0.4E +19∆
VC4(t5) = 0.6E +23∆
VC5(t5) = 0.8E −
After transition 2, the capacitor voltages should be equal to
what they were at the beginning of state 1, if the capacitor
voltages are to be balanced over each cycle. Equations (52)–
(55) show the values of the five capacitor voltages at t = t5.
Starting at t1, the converter completes a cycle at t5, and thus,
the capacitor voltages found at t5should be the same as they
were at t1.
Therefore, by comparing (24)–(27) and (52)–(55), we obtain
δ5 = −4∆
Now, the calculated values of δ1,δ3,δ4, and δ5can be proven
accurate if they satisfy the initial constraints that were made in
state 1. To check this
δ5+ δ1= −4∆
which satisfies (28), δ4− δ3− δ1=79∆
and which satisfies (29).
fore, using the computed values of δ5,δ4,δ3, and δ1, the capac-
itor voltages at the beginning of state 1 are
VC5= 0.8E −4∆
VC4= 0.6E +79∆
VC3= 0.4E +71∆
VC1= VC2= 0.2E +4∆
Here, the load voltage is VC1, and from the preceding voltage
expressions, the load voltages at different time intervals are
listed as following:
VC1(t1) = 0.2E +4∆
VC1(t2) = 0.2E −146∆
KHAN et al.: START-UP AND DYNAMIC MODELING OF THE MULTILEVEL MODULAR CAPACITOR-CLAMPED CONVERTER 527
Analytically calculated values of VC1and its variations at different
VC1(t3) = 0.2E +73∆
VC1(t4) = 0.2E −277∆
VC1(t5) = 0.2E +4∆
Using the values found from (61)–(65), the load voltages at
different time intervals were plotted in Fig. 10, and the volt-
age ripples were also estimated. It was found that at the end
of state 1, the voltage ripple was 6∆/35, and during transi-
tion 1, the ripple was −(73∆/350). During state 2, the volt-
age ripple was ∆/5, and during transition 2, the ripple was
−(57∆/350). Thus, over one full cycle, the total ripple is zero
[(6∆/35)−(73∆/350)+∆/5−(57∆/350) = 0]. Fig. 10 also
shows these ripple components at different times. Note that the
voltage quantities plotted in Fig. 10 are not to scale.
These computational steps prove that the MMCCC obtains a
stable operation when the load is connected to it. The capacitor
voltages found from (57)–(60) are the steady-state values of
them. If the converter starts with these capacitor voltages at the
beginning of state 1, after one complete cycle, the capacitor
voltages will return to these values. This steady-state operating
point will be shifted due to a change in load because the term
∆ is a function of load current. However, for different loading
conditions, the values of δ1–δ5will be different, and after one
cycle, the converter will have the same capacitor voltages that it
VI. EXPERIMENTAL VERIFICATION
A. Voltage Ripple Across the Load
To verify the voltage expression from the analytical deriva-
tion, the MMCCC was tested with different loading conditions.
Fig. 11 shows the experimental voltage across C1for a load-
ing condition described in Table IV. This experimental voltage
ripple measured across C1 is found to be consistent with the
simulated waveform, and the comparison is shown in Table IV.
The maximum percentage of error was 2.3%, which indicates
that the analytical model is accurate in estimating the LV side
Experimental values of VC1and its variations at different time
EXPERIMENTAL SETUP FOR MEASURING VC1, AND THE COMPARISON
BETWEEN ANALYTICAL AND EXPERIMENTAL RESULTS
B. Effect of Unequal Capacitors
The other useful feature of the MMCCC is the capability
of producing an accurate CR even with some variation in the
capacitances of the capacitors used in the modules. Although
the mathematical model has been derived assuming equal ca-
pacitance in every module, the MMCCC’s operation remains
unaffected when capacitors of different values are used. This
allows the MMCCC to use capacitor components that do not
have tight manufacturing tolerances. A simulation in PSIM was
performed to verify this, and three sets of data for VC1were
binations are shown in Table V, and the simulation results are
displayed in Fig. 12. This simulation shows that the MMCCC
the circuit. The simulation also shows that the ripple component
across C1is a function of the total capacitance in the circuit;
case 3 produces the largest ripple and the total capacitance was
4.1 mF, whereas it was 5 mF in both case 1 and case 2. Another
528 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 2, FEBRUARY 2010
CAPACITOR VALUES IN DIFFERENT CASES TO VERIFY MMCCC’S CAPABILITY
TO PRODUCE THE SAME CR WITH UNEQUAL CAPACITANCES
AT DIFFERENT LEVELS
of capacitances used in the circuit.
MMCCC with the loading condition described in Table V.
Simulation results of the voltages across the capacitors of the
simulation was performed to investigate the impact of loading
on the various capacitor voltages, and the results are shown in
Fig. 13. This figure shows the various capacitor voltages with
time, and the loading condition stated in Table IV was used to
generate these plots.
INPUT AND OUTPUT VOLTAGES OF THE MMCCC WITH A CONSTANT
IMPEDANCE LOAD CONNECTED AT THE LV SIDE
capacitor voltages in the MMCCC circuit.
Test schematic to characterize the impact of step load variation at the
C. Input–Output Voltage Relation
The MMCCC circuit was tested in down conversion (buck)
mode by applying various input voltages with a 2.8-Ω load
connected at the LV side. This test was performed to verify
the consistency in the CR of the converter during input volt-
age variation. Because the circuit does not have any voltage
control scheme, it maintains an integer CR, and therefore, the
output varies linearly with the input. These experimental results
are summarized in Table VI, which shows that the converter
produced a consistent CR of five except for very LV output
D. Impact of Step Load Change
When a dc–dc converter experiences a step load variation at
the output, a temporary voltage variation occurs across the load.
The variation may prolong for a considerable amount of time
CCC discussed in this paper, there was no control circuit used,
as the circuit is intended to produce constant CR regardless of
the input voltage variation. The MMCCC circuit was stressed
by a step load change at the LV side, and the voltage variations
across the various capacitors were observed and recorded. The
schematic shown in Fig. 14 was used to characterize this step
load variation and a Nicolet Vision data analyzer was used to
capture the voltage variation across the capacitors. With one
resistive load (5.8 Ω) connected at the output, the power con-
sumption was 229.4 W. The power consumption was abruptly
elevated to 510.7 W by adding a 4.2 Ω load into the circuit.
Fig. 15 shows the step ON and step OFF load changes across
the capacitors of the MMCCC. This figure also shows that the
greatest impact is experienced by C5, and the smallest voltage
variationisobservedatC1duringbothstep ONandstep OFFload
KHAN et al.: START-UP AND DYNAMIC MODELING OF THE MULTILEVEL MODULAR CAPACITOR-CLAMPED CONVERTER 529
Fig. 15.Experimental results for the capacitor voltages during a step load change. (a) Step ON. (b) Step OFF.
Fig. 16. Experimental results for the voltage fluctuations at the LV side (VC1) of the MMCCC during step load change. (a) Step ON. (b) Step OFF.
530 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 2, FEBRUARY 2010
Experimental efficiency for a 5-kW MMCCC at different loading
voltage across a capacitor is comparable for all capacitors.
The impact of a step load change at the LV side was inves-
tigated further, which is shown in Fig. 16. At 229.4 W output,
the LV side voltage was 35.66 V, and it decreased to 34.10 V
immediately after the additional load was connected to the cir-
cuit. The voltage variation is 4.37% of the steady-state value,
and the voltage returned to the previous voltage within 0.4 s.
age variation was 4.45%. Differences were observed between
the steady-state values before and after the step load change
took place. This is expected from the MMCCC circuit with-
out any voltage regulation where the steady-state output voltage
decreases with increased output power.
E. Efficiency of the MMCCC
The charge/discharge operation of the MMCCC has similar-
ities with the FCMDC. Thus, a well-constructed MMCCC with
proper current traces and appropriate components should be as
efficient as an FCMDC. Fig. 17 shows the efficiency profile of
a 5-kW MMCCC. The maximum efficiency obtained from this
circuit is 96.5%, and efficiency decays with increased load. It
was found that the 5-kW MMCCC circuit suffered from volt-
age drops across the current paths used in the circuit, and this
explains why the conduction loss in the circuit starts to domi-
nate at higher output levels. By using fast gate driving circuits,
suitable MOSFETs, and adequate current paths, the efficiency
level could be extended to the 97%–98% level for the MMCCC.
A well-designed FCMDC can achieve efficiency in the range of
96%–98% for various operating conditions .
A detailed analytical approach to calculate the capacitor volt-
Because the circuit is based on capacitor-clamped topology, the
thereby, the CR of the circuit can be determined. The analysis
and the amount of voltage ripplepresent atthe output. The start-
up analysis was simplified by reducing one variable from the
equation, and the final capacitor voltages were obtained using
eigenvalue–eigenvector decomposition. In addition, an average
current/charge model was developed, and all the capacitor volt-
capacitors exhibit charge balancing among themselves through
up and steady-state quantities were verified by experimental
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in electrical engineering from Bangladesh Univer-
sity of Engineering and Technology (BUET), Dhaka,
Bangladesh, in 1999,and theM.S degreein electrical
engineering from Arizona State University, Tempe,
in 2003, and the Ph.D. degree in electrical engineer-
ing from The University of Tennessee, Knoxville, in
Since July 2009, he has been with the Electri-
cal and Computer Engineering (ECE) Department of
University of Utah as an Assistant Professor. Prior to
joining the ECE department, he was a Senior Power Electronics Engineer at
the Electric Power Research Institute (EPRI), Knoxville from 2007–2009. His
current research interests include dc-dc converters, hybrid electric and fuel cell
automobile power management, induction generators, and vehicle battery cell
voltage management system.
Dr. Khan currently holds the Vice Chair position of the IEEE LED Lighting
Standard Committee PAR1789. He is a member of the IEEE Power Electron-
ics Society, the IEEE Industry Applications Society, and the IEEE Industrial
Electronics Society. He has served as a Reviewer and the Session Chair for
several IEEE transactions and conferences. He received the 2007 First Prize
Paper Award of the Industrial Power Converter Committee of the IEEE Industry
Leon M. Tolbert (S’88–M’91–SM’98) received the
Bachelor’s, M.S., and Ph.D. degrees in electrical
engineering from Georgia Institute of Technology,
Atlanta, in 1989, 1991, and 1999, respectively, all in
In 1991, he joined the Engineering Division, Oak
is currently a Research Engineer in the Power Elec-
tronics and Electric Machinery Research Center. In
1999, he was appointed as an Assistant Professor in
ing, The University of Tennessee, Knoxville, where he is currently the Min Kao
Professor in the Min Kao Department of Electrical Engineering and Computer
He is a Registered Professional Engineer in the state of Tennessee. Since
2007, he has been an Associate Editor of the IEEE TRANSACTIONS ON POWER
ELECTRONICS. He was the Chairman of the Education Activities Committee of
for the IEEE POWER ELECTRONICS LETTERS from 2003 to 2006. He received
the National Science Foundation (NSF) CAREER Award in 2001, and was the
recipient of the 2001 IEEE Industry Applications Society Outstanding Young
Member Award. He received two Prize Paper Awards from the IEEE Industry
Applications Society Annual Meeting.
trical engineering and computer engineering from
North Carolina State University, Raleigh, in 2004,
and the M.Sc. degree in electrical and computer
engineering from Georgia Institute of Technology,
Atlanta, in 2006.
He was a Senior Electrical Engineer for CSC Ad-
vanced Marine Enterprises, Washington, DC, where
he was engaged in providing total ship acquisition
support to several branches of the armed forces of
the United States, including the Navy, Marine Corps,
Army, and Coast Guard, and was responsible for the overall design, specifica-
tion,and integration of ships’ electrical systems, many ofwhich utilized electric
propulsion. In 2008, he joined the Electric Power Research Institute (EPRI),
where he is currently a Project Engineer and Scientist. His current research in-
terests include the design of critical power systems, including surge protection
and power conditioning.