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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 2, FEBRUARY 2010 519

Start-Up and Dynamic Modeling of the Multilevel

Modular Capacitor-Clamped Converter

Faisal H. Khan, Member, IEEE, Leon M. Tolbert, Senior Member, IEEE, and William E. Webb

Abstract—Thispaperwillpresenttheanalyticalproofofconcept

ofthemultilevelmodularcapacitor-clampedconverter(MMCCC).

Thequantitativeanalysisofthechargetransfermechanismamong

the capacitors of the MMCCC explains the start-up and steady-

state voltage balancing. Once these capacitor voltages are found

for different time intervals, the start-up and steady-state voltages

at various nodes of the MMCCC can be obtained. This analysis

provides the necessary proof that explains the stable operation of

theconverterwhenaloadisconnectedtothelow-voltagesideofthe

circuit. In addition, the analysis also shows how the LV side of the

converteris(1/N)thoftheHVsideexcitationwhentheconversion

ratio of the circuit is N. In addition to the analytical and simulation

results, experimental results are included to support the analytical

proof of concept.

Index Terms—DC–DC power conversion, power capacitors,

power conversion, power electronics, power semiconductor

switches.

I. INTRODUCTION

C

can be designed to operate at very high efficiency. The mul-

tilevel modular capacitor-clamped dc–dc converter (MMCCC)

presented in [1] had a capacitor-clamped modular architecture

unlikemanyotherdc–dcconvertersbasedoncapacitor-clamped

or charge-pump technology [2]–[15]. The MMCCC topology

has a bidirectional power management feature, and multiple

loads and sources can be simultaneously connected to this con-

verter. MMCCC’s various features and applications in hybrid

electric and fuel cell automobiles were demonstrated in [16]

and [17]. The originality and proof of concept of this topol-

ogy was verified by several simulation and experimental results

in these literatures. As the MMCCC topology is a capacitor-

clamped circuit, the proper operation and the capability to pro-

duce a certain conversion ratio (CR) can be proven by knowing

the various capacitor voltages during the start-up and steady-

state operation of the converter.

APACITOR-clamped or switched-capacitor converters

are based on capacitive energy transfer mechanisms, and

ManuscriptreceivedMay21,2008;revisedNovember25,2008andFebruary

20,2009.CurrentversionpublishedFebruary12,2010.Thisworkwassupported

by Oak Ridge National Laboratory under UT-Battelle Contract 4000007596.

Recommended for publication by Associate Editor A. Rufer.

F.H.KhaniswiththeElectricalandComputerEngineeringDepartment,Uni-

versity of Utah, Salt Lake City, UT 84112 USA (e-mail: faisal.khan@utah.edu).

W. E. Webb is with the Electric Power Research Institute (EPRI), Knoxville,

TN 37932 USA (e-mail: wwebb@epri.com).

L. M. Tolbert is with the Department of Electrical and Computer Engi-

neering, University of Tennessee, Knoxville, TN 37996-2100 USA, and also

with Oak Ridge National Laboratory, Oak Ridge, TN 37831 USA (e-mail:

tolbert@utk.edu).

Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2009.2025273

The MMCCC is inherently a bidirectional dc–dc converter.

Forthisreason,itdoesnothaveaspecificinputoroutput.Rather,

ithasanHVsideandalow-voltage(LV)side.Ifavoltagesource

ofVHVisconnectedtotheHVside,theloadconnectedattheLV

side experiences a voltage of VLV. On the other hand, a voltage

source VLVconnected at the LV side produces a load voltage of

VHVat the HV side. In both cases, VHV/VLV= N, where N is

the CR of the circuit. The schematic of a five-level MMCCC is

shown in Fig. 1.

This paper will provide the analytical derivation of the MM-

CCC voltage transfer mechanisms. The mathematical expres-

sions rely on the MMCCC circuit’s inherent nature to produce

a specific CR. In addition, several simulation and experimental

resultsareaddedtoverifytheanalyticalstart-upandsteady-state

voltage expressions derived in this paper.

II. BASIC CONSTRUCTION AND OPERATION OF THE MMCCC

The basic operation of the MMCCC has some similarities

with the flying capacitor multilevel dc–dc converter (FCMDC)

shown in [2]–[5]. It was presented in [18] that the MMCCC

exhibits some of the favorable properties of the FCMDC and

the series–parallel converter [6], [7]. The property that achieves

equal voltage stress across the transistors was adopted from the

FCMDC topology, and the modular construction was adopted

fromtheseries–parallelconverter.TheMMCCCshowninFig.1

is a five-level MMCCC, and the circuit has a CR equal to 5. The

terminology of voltage levels present in the circuit has been

used slightly differently in this paper. Usually, a multilevel dc–

dc converter with a CR equal to N is defined as an (N + 1)-

level converter. This convention was adopted from multilevel

inverters where zero voltage is a working voltage level in the

circuit.However,zerovoltagewillnotbeconsideredasavoltage

level for the MMCCC in this paper.

An N-level MMCCC circuit requires (3N − 2) transistors,

and the method of charge transfer requires two subintervals

[1] shown in Fig. 2. Compared to the FCMDC topology, the

requirement of only two subintervals, regardless of the CR of

thecircuit,makesitadvantageousfromthecontrolpointofview.

Eachtransistorwillbe ONinoneofthetwosubintervalsand OFF

in the other, which means that the transistors can be separated

into two groups that have complementary operations. In the

MMCCC shown in Fig. 1, transistors SR1–SR7 are activated in

subinterval 1 and SB1–SB6 are activated in subinterval 2.

For ease of understanding, the working principle of the MM-

CCC is discussed in the down conversion or buck mode in

this paper. In a five-level FCMDC, it takes five subintervals

to complete the power transfer operation from the input to

the output of the circuit. However, in the MMCCC, multiple

0885-8993/$26.00 © 2010 IEEE

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520IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 2, FEBRUARY 2010

Fig. 1.Schematic of a five-level MMCCC circuit with four modules.

Fig. 2.

(a) Schematic of state 1 or the first subinterval. (b) Schematic of state 2 or

the second subinterval.

Steady-state operational diagrams of a five-level MMCCC.

mutually exclusive charge–discharge operations are executed in

only two subintervals. In the first subinterval, C5 and C1 are

being charged from VHV, and C4is discharged through C3and

C1.Atthesametime,C2isdischargedtoC1.Thus,threeopera-

tions are executed simultaneously. Inthe second subinterval,C5

is discharged to C4and C1, and C3is discharged to C2and C1.

Thus,acapacitorchargedduringonesubintervalisdischargedin

the next subinterval. Although, it seems that C1is always being

charged,andnotdischargedatanysubinterval,themathematical

expression shows otherwise. It will be shown later how in each

subinterval, C1is being charged for some time, and discharged

for the remaining time in the subinterval. The charge–discharge

mechanism of various capacitors inside the MMCCC is shown

in Table I. In this table, the charge–discharge operation of the

MMCCC is also compared with a five-level FCMDC. The de-

tailed operating principle of the MMCCC can be found in [1]

and [18].

TABLE I

CHARGE–DISCHARGE OPERATION IN VARIOUS SUBINTERVALS OF AN FCMDC

AND MMCCC CONVERTER

The MMCCC circuit uses a hybrid architecture that com-

bines the favorable features of series–parallel converter and

FCMDC converter [18]. The modeling technique of various

switched-capacitorconvertershavebeendiscussedinpreviously

published literatures [2], [4], [8], [9], [19]–[28]. The MMCCC

modeling technique discussed in the following sections was not

adopted from any particular previous derivation; rather, it was

influenced by the previous works. The MMCCC circuit has two

modes of operations: dynamic state or start-up and the steady

state. Two different sets of boundary conditions are applied to

deduce the equivalent models of the operational circuit in these

two modes. Section III explains how the various capacitors at-

tain steady voltages once the converter is energized. Section IV

discusses the voltage variations of the capacitors once a load is

connected to the converter.

III. START-UP ANALYSIS OF MMCCC

The MMCCC produces a CR based on the stored and trans-

ferred charges among the capacitors. It is required to find the

capacitor voltages at different time intervals to prove the con-

cept of the MMCCC topology. The following assumptions were

made prior to the actual computational steps: 1) capacitors do

nothaveresidualvoltagesatstartup.Thisensuresthemaximum

voltage stress across the transistors and makes the analysis in

the most conservative manner, and 2) RC ? T/2, where R is the

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KHAN et al.: START-UP AND DYNAMIC MODELING OF THE MULTILEVEL MODULAR CAPACITOR-CLAMPED CONVERTER 521

Fig. 3. Start-up arrangement of a five-level MMCCC circuit.

series path resistance of a capacitor charging circuit, C is the

capacitance, and T is one switching period.

During start-up, it is also assumed that the converter is work-

ing in up-conversion (boost) mode, and the circuit is operating

without any load. Once the capacitors obtain the proper operat-

ing voltages, the converter starts operating in the steady state,

andloadscanbeconnectedtoit.Astheloaddrawscurrent,there

are variations in the capacitor voltages in both sub-intervals of

the converter [1]. These variations will depend on the load cur-

rent, operating frequency, and capacitor sizing. The second part

of the analysis works with the steady state capacitor voltages

during the two sub-intervals of the converter.

Using its bi-directional power handling capability, the MM-

CCC can seamlessly work in buck, boost or dual-source mode.

To ensure a proper charge balancing during start-up, a voltage

source of VLVis connected to the LV side of the converter, and

the HV side is left open during the start-up phase. To avoid

undesirable voltage stress across the transistors, the HV side is

not connected during the first 100 cycles of the start-up state.

It will be shown later how the capacitors attain the normal volt-

ages across them within the first 100 cycles of operation. The

transistors are operated in sequential steps with the use of a mi-

crocontroller. Fig. 3 shows the schematic of the MMCCC with

the required arrangement for start-up operation, and Table II

shows the required transistor operation for the start-up steps.

Step 3 and step 4 in Table II are repeated 100 times to ensure

appropriate voltage build up across the capacitors. If the circuit

works without any loss or voltage drop across any active or pas-

sivedevices,afive-levelMMCCCwillhaveaVHV/VLVratioof

5. At steady state, the capacitors should have voltages like the

following to ensure equal voltage stresses across the transistors:

VC1= VLV,

VC5= 4VLV,

VC2= VLV,VC3= 2VLV,

VHV= 5VLV.

VC4= 3VLV,

and

Thus, if the capacitor voltages are found in this form at the

end of the modeling, it indicates that the MMCCC circuit can

produce the expected CR.

TABLE II

ACTIVE TRANSISTORS AND CAPACITORS IN THE START-UP STEPS

A. Step 1 of the Start-Up Process

The operation of this step is shown in Fig. 4(a). In this step,

capacitors C1and C2are connected to the VLV source. Thus,

the voltage equations of the capacitors would be

VC1(t1) = VC2(t1) = VLV

VC3(t1) = VC4(t1) = VC5(t1) = 0.

(1)

(2)

B. Step 2 of the Start-Up Process

This step involves the discharging operation of C2and the

charging operation of C3. The operation is shown in Fig. 4(b).

Therefore

VC1(t2) = VLV

(3)

VC2(t2) = VC2(t1) + [VLV+ VC2(t1) − VC3(t1)]

= 0.5[VC2(t1) + VC3(t1) + VLV]

C3

C2+ C3

(4)

VC3(t2) = VC3(t1) + [VLV+ VC2(t1) − VC3(t1)]

= 0.5[VC2(t1) + VC3(t1) + VLV]

VC4(t2) = VC5(t2) = 0.

C2

C2+ C3

(5)

(6)

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522 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 2, FEBRUARY 2010

Fig.4.

(a) Step 1. (b) Step 2. (c) Step 3. (d) Step 4.

Schematicdiagramofthestart-upstepsofafive-levelMMCCCcircuit.

C. Step 3 of the Start-Up Process

The operational diagram of this step is shown in Fig. 4(c). In

this step, the charge is transferred from C3to C4. C2is again

connected to VLVas in step 1. Thus, the voltage equations are

given as

VC1(t3) = VC2(t3) = VLV

VC3(t3) = 0.5[VC3(t2) + VC4(t2) − VLV]

VC4(t2) = 0.5[VC3(t2) + VC4(t2) + VLV]

VC5(t3) = VC5(t2) = 0.

(7)

(8)

(9)

(10)

D. Step 4 of the Start-Up Process

This step involves the operations that took place in step 2

with an additional charge transfer action from C4to C5. The

operational diagram of step 4 is shown in Fig. 4(d), and the

voltage equations are given as

VC1(t4) = VLV

VC2(t4) = 0.5[VC2(t3) + VC3(t3)] − 0.5VLV

VC3(t4) = 0.5[VC2(t3) + VC3(t3)] + 0.5VLV

VC4(t4) = 0.5[VC4(t3) + VC5(t3)] − 0.5VLV

VC5(t4) = 0.5[VC4(t3) + VC5(t3)] + 0.5VLV.

(11)

(12)

(13)

(14)

(15)

Using (1)–(4), the capacitor voltages at the end of step 2 are

X0=

VC1

VC2

VC3

VC4

VC5

=

VLV

0

VLV

0

0

.

(16)

The values found from (16) will be used as the initial condi-

tions for step 3, and the voltages at the end of step 3 will be used

as the initial voltages for step 4. From the operating principle of

the converter, all odd indexed steps become equivalent once the

circuit completes the first four steps. This is also true of all even

indexed steps. Thus, the circuit is modeled using two repetitive

operations described in step 3 and 4. A variable k is defined

where k starts from 2. Therefore, the capacitor voltages in any

odd and even indexed steps can be generalized using (7)–(10)

and (11)–(15), and can be expressed in the following matrix,

shown in (17) and (18) at the bottom of this page.

Here, (17) and (18) are in the form y = Mx + b and z =

Ny + d. After doing the matrix manipulation and expressing

the constant factors in terms of VC1, shown in (19) and (20) at

the bottom of the next page, where

VC1(k) = VC1(k + 1) = VC1(k + n) = VLV.

VC1(k + 1)

VC2(k + 1)

VC3(k + 1)

VC4(k + 1)

VC5(k + 1)

=

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0.5

0.5

0

0.5

0.5

0

VC1(k)

VC2(k)

VC3(k)

VC4(k)

VC5(k)

+

1

1

−0.5

0.5

0

VLV

(17)

VC1(k + 2)

VC2(k + 2)

VC3(k + 2)

VC4(k + 2)

VC5(k + 2)

=

0

0

0

0

0

000

0

0

0

0

0

0.5

0.5

0

0

0.5

0.5

0

0

0.5

0.5

0.5

0.5

VC1(k + 1)

VC2(k + 1)

VC3(k + 1)

VC4(k + 1)

VC5(k + 1)

+

1

−0.5

0.5

−0.5

0.5

VLV.

(18)

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KHAN et al.: START-UP AND DYNAMIC MODELING OF THE MULTILEVEL MODULAR CAPACITOR-CLAMPED CONVERTER 523

After n iterations, the final capacitor voltage vector can be

given by

f = (CA)nX0

(21a)

where X0is the capacitor voltage matrix at the end of step 2

found in (16). Using MATLAB

and the final capacitor voltage matrix f can be calculated using

(21a) and (21b). Thus,

The start-up gating sequence is operated at a speed of

10000 steps/s, which is equal to the switching frequency

(10 kHz) of the converter at steady state. Thus, after 100 it-

erations or 10 ms

VC1= 1VLV

VC2= 1VLV

VC3= 2VLV

VC4= 3VLV

VC5= 4VLV.

The analytical derivation presented in this section explains

the start-up operation of a five-level MMCCC circuit. In Fig. 2,

the two subintervals of the circuit in steady state are shown.

In the first subinterval, C5and C1are connected in series and

acrossVHV.Ifthereisnolossinthecircuitoranyloadconnected

attheoutput,thetotalvoltageacrosstheseriesconnectedcircuit

ofC5andC1shouldbe5VLV,asshownin(23).Inaddition,there

is another current path composed of C4,C3, and C1. In Fig. 2,

during state 1, C4is connected across the series combination

of C3and C1. Equation (23) shows that the voltage across C4

(3 VLV) is equal to the summation of voltages across C1(1 VLV)

and C3(2 VLV). Moreover, C2is connected across C1, and their

(CA)n=

1

1

2

3

4

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

,

where n = 100

(21b)

f =

1

1

2

3

4

VLV.

(22)

(23)

Fig. 5.

n = 40, all voltages have reached steady state for all practical purposes. Voltage

magnitudes are normalized to VLV. Each iteration takes 100 µs.

Analytically derived capacitor voltage variations with iterations. At

voltages are also matched. Therefore, the voltages across the

capacitors during state 1 are matched to each other.

In state 2, C5is connected across the series circuit of C4and

C1. These voltages are also matched and can be seen in (23). In

thesameway,C3isconnectedacrosstheseriescircuitofC2and

C1, and the voltage across C3(2 VLV) is the same as the total

voltage across C1and C2(VLV+ VLV= 2VLV). Therefore, the

capacitorvoltagesinstate2arealsomatched,andtheloadcanbe

connectedeitheratHVsideorLVside.Oncealoadisconnected

at either side, the load current will discharge the capacitors, and

charge transfer willtake place either from a voltage source (VLV

or VHV) to a capacitor or from one capacitor to another. In this

case, the steady-state capacitor voltages will be different from

the values stated in (23), and the analysis is shown in the next

section.

The values of different capacitor voltages in (21a) were plot-

ted for different values of n varying in the range of 1 to 100,

as shown in Fig. 5. Two charge transfer operations in odd and

even indexed steps [shown in (19) and (20)] take place in one

clock cycle (for one value of n), and Fig. 5 shows the capacitor

voltages attheendoftheeven indexed step(second subinterval)

ineachclockcycle.Itisalsoseenthat,forallpracticalpurposes,

the capacitor voltages reach steady state after 40 iterations. To

verify the start-up operation using the technique presented in

VC1(k + 1)

VC2(k + 1)

VC3(k + 1)

VC4(k + 1)

VC5(k + 1)

=

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

1

−0.5

0.5

0

0.5

0.5

0

0.5

0.5

0

VC1(k)

VC2(k)

VC3(k)

VC4(k)

VC5(k)

= A

VC1(k)

VC2(k)

VC3(k)

VC4(k)

VC5(k)

= C

VC1(k + 1)

VC2(k + 1)

VC3(k + 1)

VC4(k + 1)

VC5(k + 1)

= AX0

(19)

VC1(k + 2)

VC2(k + 2)

VC3(k + 2)

VC4(k + 2)

VC5(k + 2)

=

1000

0

0

0

0

0

−0.5

0.5

−0.5

0.5

0.5

0.5

0

0

0.5

0.5

0

0

0.5

0.5

0.5

0.5

VC1(k + 1)

VC2(k + 1)

VC3(k + 1)

VC4(k + 1)

VC5(k + 1)

(20)