We propose an asymmetric-MOSFET-based six-transistor (6 T) SRAM cell to alleviate the conflicting requirements of read and write operations. The source-to-drain and drain-to-source characteristics of access transistors are optimized to improve writability without sacrificing read stability. The proposed technique improves the writability by 9%-11%, with iso read stability being compared with a conventional 6 T SRAM cell based on symmetric-MOSFET access transistors in 45-nm technology.
[Show abstract][Hide abstract] ABSTRACT: We propose FinFETs with unequal source and drain doping concentrations [asymmetrically doped (AD) FinFETs] for low-power robust SRAMs. The effect of asymmetric source/drain doping on the device characteristics is extensively analyzed, and the key differences between conventional and AD FinFETs are clearly shown. We show that asymmetry in the device structure leads to unequal currents for positive and negative drain biases, which is exploited to achieve mitigation of read-write conflict in 6T SRAMs. The proposed device exhibits superior short-channel characteristics compared to a conventional FinFET due to reduced electric fields from the terminal that has a lower doping. This results in significantly lower cell leakage in AD-FinFET-based 6T SRAM. Compared to the conventional FinFET-based 6T SRAM, AD-FinFET SRAM shows 5.2%-8.3% improvement in read static noise margin (SNM), 4.1%-10.2% higher write margin, 4.1%-8.8% lower write time, 1.3%-3.5% higher hold SNM, and 2.1-2.5 lower cell leakage at the cost of 20%-23% higher access time. There is no area penalty associated with the proposed technique.
IEEE Transactions on Electron Devices 01/2012; 58(12-58):4241 - 4249. DOI:10.1109/TED.2011.2169678 · 2.47 Impact Factor
"In other words, the DIBL of the drain side measurement is more prominent than the source side. The modification in DIBL effect is not the only case for the proposed local electron injection scheme but also for the conventional asymmetric halo doping scheme , . "
[Show abstract][Hide abstract] ABSTRACT: A V <sub>TH</sub> mismatch self-repair scheme in 6T-SRAM with asymmetric pass gate transistor by post-process local electron injection is proposed. Local electron injection is automatically and simultaneously achieved to either pass gate transistor that most increases the read margin for each cell without investigating its characteristics. The proposed asymmetric V <sub>TH</sub> shift is twice as large as the conventional scheme without process and cell area penalty. Measurement results show 20% increase in SNM without write degradation by the asymmetric PG transistor. The proposed scheme also enhances the minimum read margin by 70% while reducing read margin distribution by 20%, thanks to the self-repair function.
[Show abstract][Hide abstract] ABSTRACT: We present a 0.5 V 6T SRAM fabricated in a 90 nm PD-SOI technology with asymmetric MOSFET to improve the read and write margin. The design also uses a forward-body-bias technique in the bit-cell and peripheral circuits. The measured minimum operating voltage of the SRAM is 0.45 V at 25Â°C, which is 100 mV lower than conventional SRAM. The access time is 6.8 ns at 0.5 V.
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