Relaxing Conflict Between Read Stability and Writability in 6T SRAM Cell Using Asymmetric Transistors

IBM T J. Watson Res. Center, Yorktown Heights, NY, USA
IEEE Electron Device Letters (Impact Factor: 3.02). 09/2009; DOI: 10.1109/LED.2009.2024014
Source: IEEE Xplore

ABSTRACT We propose an asymmetric-MOSFET-based six-transistor (6 T) SRAM cell to alleviate the conflicting requirements of read and write operations. The source-to-drain and drain-to-source characteristics of access transistors are optimized to improve writability without sacrificing read stability. The proposed technique improves the writability by 9%-11%, with iso read stability being compared with a conventional 6 T SRAM cell based on symmetric-MOSFET access transistors in 45-nm technology.

  • [Show abstract] [Hide abstract]
    ABSTRACT: A statistical threshold voltage VTH shift variation of the pass gate (PG) transistor in local electron injected asymmetric PG transistor 6T-SRAM is investigated. Measurements show that the positive correlation between the PG transistor VTH shift (VTHPG shift) and its original VTH of the PG transistor (VTHPG) before injection due to VD effect is self-compensated by the negative correlation between those by ID effect. As a result, the measured VTHPG shift is less correlated with the VTHPG before electron injection. Therefore, near VTH word-line (WL) voltage injection self-convergence scheme is proposed to avoid VTHPG shift in the high VTHPG cell and enhance in the low VTHPG cell. By the proposed scheme, VD effect is reduced and ID effect is enhanced. The improved negative correlation factor is observed between the VTHPG shift and the forward VTHPG before injection. R2 is increased by 21 times by the proposed scheme. As a result, excess write margin degradation is suppressed. Furthermore, the fabricated 64 kb SRAM macro demonstrates 3 times larger WL operation voltage window, 41% less read margin variation and 80 mV lower VCCMIN after the local electron injection.
    Circuits and Systems I: Regular Papers, IEEE Transactions on 08/2012; 59(8):1635-1643. · 2.30 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: A post-process carrier injection scheme for 6T-SRAM is proposed. The proposed scheme pinpoints and simultaneously repairs only cells that have low read disturb margin by injecting electrons to the strong pass gate transistor. Compared with the conventional electron injection scheme that injects electrons to either side of the pass gate transistor of all cells, the proposed scheme achieves 57% less BL delay, 31% less read energy, 32 ~ 256 times shorter injection time and 3% area reduction. The concept is validated with 2, 64, 128 kb SRAM in 40 nm standard CMOS process. Experiments show around 40 mV operation margin increase after the proposed injection.
    IEEE Journal of Solid-State Circuits 01/2013; 48(9):2239-2249. · 3.11 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: We propose SRAM bitcells with asymmetric halo implant dose MOSFET (AH-MOS) by introducing additional masks for halo implant steps. AH-MOS has different drain-source currents (Ids) between forward and reverse directions (Fig. 1). By implanting high and low dose for drain and source regions respectively, Ids flowing from drain to source (forward) gets larger than that from source to drain (reverse). Fig. 2 shows 6T SRAM bitcell with AH-MOS [1]. The current at pass-gate (PG), which consists of AH-MOS, flows bi-directionally in read and write mode. The pull-down (PD) is symmetric halo implant dose MOSFET (SH-MOS) due to unidirectional currents. The pull-up (PU) is also SH-MOS.