Relaxing Conflict Between Read Stability and Writability in 6T SRAM Cell Using Asymmetric Transistors
ABSTRACT We propose an asymmetric-MOSFET-based six-transistor (6 T) SRAM cell to alleviate the conflicting requirements of read and write operations. The source-to-drain and drain-to-source characteristics of access transistors are optimized to improve writability without sacrificing read stability. The proposed technique improves the writability by 9%-11%, with iso read stability being compared with a conventional 6 T SRAM cell based on symmetric-MOSFET access transistors in 45-nm technology.
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ABSTRACT: The physics, technology, and modeling of complementary asymmetric MOSFETs are reviewed and illustrated with statistically representative silicon data from a recent manufacturing implementation, in which the transistors for the secondary power supply voltage are offered in asymmetric and symmetric constructions. The in-depth analysis of the device physics of asymmetric transistors provides new insights into their physical operation and into the operation of transistors using halo implants in general. The variability, matching, and noise implications of using halo implants are also analyzed, concluding that both asymmetric and symmetric devices need to be offered for uncompromised circuit design. The challenges associated with the compact modeling the asymmetric transistors are also reviewed and illustrated. The preferred manufacturing implementation uses retrograde wells with no dopant fillers at the surface, while avoiding the drain-to-source punch-through by source-side-only halo implants. In addition to the known switching speed and maximum voltage gain advantages of the asymmetric transistors, this particular device architecture offers superior hot-carrier reliability and transistor design flexibility. The availability of retrograde wells enables construction of high-reliability complementary extended-drain MOSFETs for a third higher power supply voltage.IEEE Transactions on Electron Devices 01/2010; 57(10):2363-2380. · 2.06 Impact Factor
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ABSTRACT: We present a 0.5 V 6T SRAM fabricated in a 90 nm PD-SOI technology with asymmetric MOSFET to improve the read and write margin. The design also uses a forward-body-bias technique in the bit-cell and peripheral circuits. The measured minimum operating voltage of the SRAM is 0.45 V at 25Â°C, which is 100 mV lower than conventional SRAM. The access time is 6.8 ns at 0.5 V.Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International; 03/2010
Conference Paper: A dynamic body-biased SRAM with asymmetric halo implant MOSFETs[Show abstract] [Hide abstract]
ABSTRACT: In this paper, we propose an SRAM macro that realizes 0.5V operation by combining a device technique with simple design architecture. Regarding the device technique, we utilize asymmetric halo implant MOSFETs, which enables to enhance both the static noise margin and write margin of SRAM, simultaneously. As for the design technique, dynamic body-bias scheme which operates body bias dynamically is introduced to overcome the speed degradation due to lower supply voltage. Showing measured data fabricated on 45nm CMOS technology, we demonstrate a plausible scenario for achieving 0.5V operating SoC products.Low Power Electronics and Design (ISLPED) 2011 International Symposium on; 09/2011