Relaxing Conflict Between Read Stability and Writability in 6T SRAM Cell Using Asymmetric Transistors

IBM T J. Watson Res. Center, Yorktown Heights, NY, USA
IEEE Electron Device Letters (Impact Factor: 3.02). 09/2009; 30(8):852 - 854. DOI: 10.1109/LED.2009.2024014
Source: IEEE Xplore

ABSTRACT We propose an asymmetric-MOSFET-based six-transistor (6 T) SRAM cell to alleviate the conflicting requirements of read and write operations. The source-to-drain and drain-to-source characteristics of access transistors are optimized to improve writability without sacrificing read stability. The proposed technique improves the writability by 9%-11%, with iso read stability being compared with a conventional 6 T SRAM cell based on symmetric-MOSFET access transistors in 45-nm technology.

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