Verification of analog and mixed signal designs using online monitoring

Abstract

Analog and mixed signal (AMS) circuits play an important role in today's System on Chip design. They pose, however, many challenges in the verification of the overall system due to their complex behavior. Among many developed verification techniques, runtime verification has been shown to be effective by experimenting finite executions instead of going through the whole state space. In this paper, we present a methodology for the specification and verification of AMS designs using online monitoring at runtime based on the notion of System of Recurrence Equations (SREs). We implement the proposed methodology in a C language based tool, called C-SRE, and utilize it to verify several properties of a PLL design. We compare our proposed online monitoring techniques with the offline approach. Finally, we apply the proposed methodology to monitor the jitter noise associated with a voltage controlled oscillator.

Full text

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Verification of Analog and Mixed Signal Designs
using Online Monitoring
Zhiwei Wang1, Naeem Abbasi1, Rajeev Narayanan1,
Mohamed H. Zaki2, Ghiath Al Sammane1, and Sofi` ene Tahar1
1Dept. ECE, Concordia University, Montreal, Quebec, Canada
Email: {zhiw wan, n ab, r naraya, sammane, tahar}@ece.concordia.ca
2Dept. CS, University of British Columbia, Vancouver, British Columbia, Canada
Email: mzaki@cs.ubc.ca
Abstract—Analog and mixed signal (AMS) circuits play an
important role in today’s System on Chip design. They pose,
however, many challenges in the verification of the overall
system due to their complex behavior. Among many developed
verification techniques, runtime verification has been shown to
be effective by experimenting finite executions instead of going
through the whole state space. In this paper, we present a
methodology for the specification and verification of AMS designs
using online monitoring at runtime based on the notion of System
of Recurrence Equations (SREs). We implement the proposed
methodology in a C language based tool, called C-SRE, and utilize
it to verify several properties of a PLL design. We compare our
proposed online monitoring techniques with the offline approach.
Finally, we apply the proposed methodology to monitor the jitter
noise associated with a voltage controlled oscillator.
I. INTRODUCTION
With the prominent evolution of semiconductor industry,
more and more System on Chip (SoC) architectures are
utilized in embedded systems. The design of Analog and
Mixed Signal (AMS) components, which connect the physical
world to digital space, plays an important role in SoC design.
Traditionally, the verification of AMS designs is carried
out using simulation to validate basic specifications. However,
with this approach it is not possible to experiment all the
combinations of inputs. For this purpose, formal methods,
such as model checking, have recently been employed for
the verification of AMS designs [17]. Model checking is
capable of validating the system by proving that the behavior
of the circuit satisfies a set of properties. Unfortunately, model
checking of AMS circuits is computationally expensive in
terms of memory and CPU time and suffers from the state
space explosion problem as well as long processing time which
make exhaustive verification very hard [17].
In order to overcome the above mentioned limitations,
runtime verification, which integrates program execution and
formal methods, has been advocated. Runtime verification
is a technique for checking whether an execution of the
design model violates the design specifications (properties).
Instead of exhaustively walking through the state space, run-
time verification considers finite executions. Consequently, the
computational resources and simulation time are saved dramat-
ically. There are two types of monitoring techniques [11]: (1)
978-1-4244-4617-9/09/$25.00 ©2009 IEEE
Online monitoring, where the properties are observed while the
simulation is running, and hence the violation or satisfaction
of a property can be detected as soon as it occurs; (2) Offline
monitoring, where the properties are checked based on the
results stored at the end of the simulation. Online monitoring
costs less than offline by saving the space required for storage
of simulation results. Moreover simulation time is also saved
instead of running the whole simulation cycle.
In this paper, we propose an online monitoring approach
for the verification of AMS designs based on the notion of
Sequence of Recurrence Equations (SRE) [16]. SREs are a
form of difference equation used to model both the AMS
design under verification as well as the properties to be
monitored. We have implemented an SRE based simulator
to monitor specifications in PSL (Property Specification
Language) standard [2], which we translate into SREs. To
illustrate the feasibility of the proposed approach, we have
experimented with checking of several properties on a PLL
(Phase-Locked Loop) design as case study.
Related Work. The verification of AMS designs using
monitoring has attracted a lot of attentions in recent years.
The most prominent work is presented in [10], where the
authors presented an offline methodology for monitoring the
simulation of continuous signals. The monitoring technique
was based on an extension of PSL to support analog signals.
The PSL extension was synthesized into timed automata
to check for property violation of simulation traces using
Matlab. To demonstrate their approach, a tool AMT [14] was
built to support monitoring in both offline and incremental
fashion. This incremental procedure checks the simulation
traces only upon changes in the input signals, rather than in
an online fashion. This approach synthesizes the property in
terms of lower abstraction such as timed automata and FSM.
In this paper, we propose a higher level of abstraction and
a unified framework for both modeling and monitoring of
AMS designs.
In [6], an online monitoring technique is proposed, where
the authors take advantage of linear hybrid automata as
monitor to analyze the reachability of time domain features;
signal amplitude and jitter of an oscillator circuit were studied.

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The work in [6] assumes the existence of templates to build
the monitor. It does not provide a generic way to obtain the
monitors from the specification. In contrast to [6], the approach
we advance is capable of modeling and monitoring the AMS
design and supports PSL as specification language. In a related
work, an FPGA implementation of assertion based monitor
is presented in [13]. The authors utilize PSL to generate an
asynchronous monitor which is robust to process, temperature
and voltage variations. Moreover, the online monitoring is
suitable for ASIC designs. Nevertheless, the work in [13] was
unable to support both analog and mixed signal circuits nor
SERE expressions in PSL.
A more recent work in [7] introduces a methodology to
define mixed signal assertions (MSA) for verification by
combining PSL and STL (Signal Temporal Logic) [14], where
the specifications for digital and analog parts are translated
into PSL and STL, respectively, as either precondition or
postcondition. An MSA then is constructed by combining the
precondition and postcondition with an implication. Assertion
based verification or formal verification could be carried out
due to the formalized properties. The authors applied the MSA
to a first order Σ/∆ converter and several properties were
checked. The work was validated within the MLDesigner [12]
tool with an enhanced assertion monitoring library. Instead, in
this paper, one single formalism, namely SRE, is employed
to express PSL properties both for analog and digital part.
Additionally, we offer a whole package including simulator
and monitor. In [16], an offline assertion based verification is
introduced, where SREs are used to model the AMS design.
Our work is different from [16] in two aspects. First, we
use online monitoring to achieve verification. Secondly, we
present a tool, named C-SRE, which simulates AMS designs
modeled with SREs, reads PSL properties and realizes the
online monitoring.
The rest of the paper is organized as follows: in Section
II, we briefly review the fundamental notions of SRE and
PSL and describe how PSL properties can be expressed using
SRE. In Section III, we introduce our online monitoring
methodology for AMS design verification along with the SRE
based simulator. The Section IV is dedicated to the modeling
of PLL using SRE. The experimental results on verification of
a PLL design are illustrated in Section V. Finally, Section VI
concludes the paper.
II. PRELIMINARIES
A. System of Recurrence Equations (SRE)
A recurrence equation or a difference equation is the dis-
crete version of an analog differential equation. A recurrence
equation defines a relation between consecutive elements of
a sequence. In [16], the notion of recurrence equation is
extended to describe digital circuits as follows: Consider a
set of variables Xi
Xi(n) = fi(Xj(n − γ)),(j,γ) ∈ ?i,∀n ∈ Z
where fi(Xj(n−γ) is a generalized If-formula which is
either a variable, an arithmetic operation, a logical formula, a
comparison formula or an If-Then-Else expression [16]. The
set ?iis a finite non empty subset of 1,...,k×N. The integer
γ is called the delay.
A given AMS design consists of blocks both in analog and
digital. For digital blocks, the SRE can be expressed directly
from their logic functions. For continuous time components,
we have two possible ways to generate recurrence equations.
First, we can write the recurrence equation based on time
domain differential algebraic equations through discretization.
The second method is using Impulse-Invariant z transforma-
tion to find a discrete time approximation of the continuous
time transfer function. Then, we apply the inversion of z
transform to generate difference equation and convert it into
recurrence equation [1].
B. PSL in SREs
As an assertion language, PSL contains four layers [4]:
Boolean, temporal, verification and modeling layer. The ver-
ification layer provides the communication and interaction
between the properties and the verification tool. The modeling
layer is used to defined the verification environment for the
tool. The Boolean layer constructs the basic expressions for
the property. The temporal layer, where the temporal relations
between the signals are expressed, is the heart of PSL. PSL
exhibits the property with either linear logic or branching
logic. The Foundation Language (FL) is used to express the
sequences of the states of the property and the Optional
Branching Extension (OBE) is used to interpret the tree of
states [2]. However, these languages deal with digital design
verification. Due to the presence of analog signals in AMS
designs, it is difficult to monitor analog properties in PSL.
In order to overcome this obstacle, we propose to rewrite
the PSL property into SRE notation. The consistency between
the design and the properties allows us to observe the design
specifications while running the simulation. The Boolean layer
specifies propositions, from the design and signals, which
evaluate to the Boolean value true or false in a simulation
cycle. The signals of AMS systems may feature continuous
time natures. In PSL the analog description to a Boolean
variable is an inequation which is built using signals and
registers of the AMS design [16]. This expression is defined
as the Basic Property [16]:
Let x be the name of an AMS signal (or register), a basic
property p is a logical formula defined as follows: p = x ? y,
where ? ∈ {<,≤,>,≥,=,?=} and y is a value, a name of a
signal (or a register) in the design or an arithmetic function
built using the design signals.
Let p be a basic property. For each signal (or register) x,
y in the basic property we associate a time instance of the
form x(n), where n ∈ Z. This instance corresponds to the
evaluation of the recurrence equation representing this value
at time n. We call p(n) the Trace of the Basic Property of
p. The nature of n depends on the SERE or temporal layer
operator preceding the basic property. It can be either a
numerical constant value, or a symbolic constant value, or a
time variable [16].

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III. METHODOLOGY
In this section, we first present the online monitoring
methodology for AMS design verification, followed by details
of the SRE based simulator we use.
A. Online Monitoring Methodology
The online monitoring based runtime verification method-
ology we propose is shown in Figure 1. The AMS design
is modeled using SRE based on the circuit description and
implemented into our simulator (C-SRE). Design properties
are expressed in PSL. The PSL expression is converted to
SRE notation. Finally, the input stimulus and output traces
are delivered to the monitor. The monitor evaluates the inputs
and outputs of the simulator and checks whether the behavior
satisfies the design specification. The monitoring is performed
in an online fashion which means if the property is satisfied,
the monitor reports the satisfaction; otherwise, the monitor
terminates the simulation at the cycle when the violation
occurs. The input stimulus includes the input signal of the
system and environment such as control signals. The output
trace from the simulator can be either the system output or
the output from any component within the system. The AMS
specifications we focus on in this paper are written in temporal
logic. Hence, we use PSL to express the property initially
and then convert it to SRE notation. The evaluation on the
relation between input and output with the design specification
is carried out within the monitor.
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INPUT
TRACE
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OUTPUT
TRACE
PROPERTY
PROPERTY VIOLATED
PROPERTY VERIFIED
Fig. 1.Proposed Verification Methodology
The monitor is used to check whether the current simulation
behavior satisfies a given correctness property. Based on the
definitions of Basic Property and Trace of Basic Property [16],
the properties in PSL can be observed by translating them
into recurrence sequence notations. In our methodology, the
input and output traces are provided to the monitor at each
simulation time instant. Incorporated with the property checker
described above, at each time instant of the simulation, the
property satisfaction is checked. The process is carried out
as long as no violation is detected within enough simulation
length. Moreover, by taking advantage of the C-SRE simulator
(described in Section III-B) which records all the transient
data of all circuit blocks at runtime, the monitor is capable of
observing the property of individual block.
B. C-SRE Simulator
The proposed modeling technique and online monitoring are
implemented in a tool named C-SRE1. Figure 2 shows the C-
SRE simulator framework. The C-SRE tool basically solves a
system of recurrence equations describing the behavior of an
analog and mixed signal system. There are four main inputs
to the tool: (1) The AMS design behavior described using
continuous-time (CT), discrete-time (DT) and discrete-events
(DE) SRE notations; (2) PSL properties, in SRE notations,
expressed using C language; (3) Various inputs and initial
conditions to the design; and (4) Simulation parameters such
as minimum and maximum time step sizes, and simulation
duration etc. The tool output contains the result of executing
the monitor in an online fashion, along with various supporting
signal traces for easy visualization of the results.
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C-SRE Simulator Framework
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The C-SRE solver is the core of the simulator. It guarantees
that the CT, DT or DE SREs are executed at an appropriate
instant of time to simulate the correct transient behavior of
the circuit. The scheduling algorithm is explained below: Let
TCT, TDTand TDEbe the continuous time, discrete time, and
discrete event time steps, respectively. If we assume that TCT
is always the smallest time step taken during the simulation,
we can achieve both a desired time resolution and accuracy.
TDT is uniformly spaced in time and is known in advance.
The remaining two time step sizes are determined dynamically
during the simulation. In an AMS design, those three processes
may interact with each other. The discrete-time part of the
design only interacts at intervals of TDT with the other parts.
The simulation time advances by following four rules given
below:
• If TCT = TDT and TCT = TDE then update the DE and DT
SREs
• If TCT = TDT and TCT < TDE then update the DT SREs
• If TCT < TDT and TCT = TDE then update the DE SREs
• If TCT < TDT and TCT < TDE then update the CT SREs
where tCT = tCT+ TCT,tDT = tDT+ TDT,tDE= tDE+
TDE and Tcurrent = MIN(tDT,tCT,tDE). Figure 3 illus-
trates example time instants at which continuous-time (circle),
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Fig. 2.
1The simulator is named C-SRE because all the components of the
simulator are coded in C/C++.

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Tcurrent
1
22
3
4
5
6
7
8
9
10
1112
13
14
15
16
17
18
19
20
tCT
tDT
tDE
Fig. 3.Timing Diagram
discrete-time (triangle), and discrete-event (square) SREs have
to be executed so as to simulate the correct behavior of
the system. The numbers in the figure show the sequence
of operations. The discrete time steps (triangle) are equally
spaced where as the continuous time (circle) and discrete event
(square) time steps are determined dynamically during the
simulation. The simulation starts with initialization and then
proceeds guided by the scheduling algorithm. It terminates
when the current simulation time (Tcurrent) either exceeds
or becomes equal to the maximum simulation time. The
algorithm described above guarantees that SREs execute in
proper sequence in order to simulate the correct behavior of
the circuit. For detailed description of the C-SRE simulator,
please refer to [1].
In the following sections, we present, respectively, the
SRE modeling and runtime verification of a PLL frequency
synthesizer as a case study.
IV. PLL MODELING USING SRE
A Phase Locked Loop (PLL) is one of the basic AMS
building blocks in modern communication systems. A PLL
based frequency synthesizer model, as shown in Figure 4, is
composed of a comparator (COMP), a phase and frequency
detector (PFD), a charge pump (CP), an analog filter (AF), a
voltage controlled oscillator (VCO) and a divider (DIV) [3]. If
the frequency control signal Freq sel is set to 0, the frequency
of the reference input and VCO output will be the same. If
Freq sel is set to 1, the VCO output frequency is two times
as the reference signal.
Ref_pf
d
UP
DN
Charge_outFilter_out
VCO_out
VCO_out_div1
VCO_pfd
Freq_sel
AF
VCO
CPPFD
DIV
COMP
0
COMP
Ref_sig
0
Fig. 4.PLL Frequency Synthesizer
In the following, we briefly describe the SRE models of
the important blocks. Please refer to [1] for a full description
of PLL in SRE.
Comparator
The comparator extracts the positive value of the input and
generates binary sequence with the same frequency as the
input. The comparator is a mixed signal component as the
input is analog and the output is digital. The SRE model of
the comparator is given by
Ref_pfd(n+1) = IF(Ref_sig(n) ≥ 0, 1, 0)
Ref_sig(n) = sin(ω0nT)
where Ref sig is one of the inputs to the comparator.
Phase and Frequency Detector
The phase and frequency detector (PFD) shown in Figure 5
is a pure digital block of the PLL system. Two input signals
VDD
D
CK CK
Q
Ref pfd_p
UP
RResett
CK
DD
Q
VCO_pfd
DN
V VDD
Fig. 5.Phase and Frequency Detector
Ref pfd and V CO pfd, which are the reference signal
and the feedback signal from VCO output and the divider,
respectively, act as the clocks of two flipflops. Each input
triggers at its rising edge and propagates the supply voltage
from data port D to output port Q. The outputs of interest,
UP and DN, reflect the difference in both frequency and
phase between the two input signals. When UP and DN are
simultaneously high, the AND gate resets both flipflops. The
rising edge trigger behavior can be express in SRE as:
UP(n+1) = IF{[UP(n)=1 ∧ DN(n)=1],
0,IF[Ref_pfd(n)=1∧Ref_pfd(n-1)=0,1,UP(n)]}
DN(n+1) = IF{[UP(n)=1 ∧ DN(n)=1],
0,IF[VCO_pfd(n)=1∧VCO_pfd(n-1)=0,1,DN(n)]}
Two If-formula SRE expressions are nested to model
the PFD. The outer SRE identifies the reset condition. The
inner one generates the difference of frequency and phase
according to the rising edge of the input signal.
Charge Pump
The charge pump is usually interposed between the PFD
and the analog filter to provide voltage or current for the
capacitance in the successive filter. In this case study, we
adopt the voltage VC as source supply. The resulting source
supply is proportional to the difference of the output signal
UP and DN from PFD. The SRE model of the charge pump
is given by
Charge_out(n) = VC × [UP(n-1) - DN(n-1)]

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The SRE of the charge pump is the difference equation of
the functionality.
Analog Filter
An analog filter is usually constructed by combining
resistances and capacitances. In our frequency synthesizer,
a simple first order lowpass filter is employed. The
implementation of the analog filter is shown in Figure 6.
++
++
R
Filter_outCharge_out
C
-
-
Fig. 6. First Order Lowpass Filter
When modeling an analog filter, we are given the transfer
function in frequency domain as:
H(s) =
1
1 +
s
ωc
(1)
where ωc =
filter. After applying Impulse-Invariant z transform [3], we
obtain the z domain transfer function:
1
RC. ωc is the cutoff frequency of the lowpass
H(z) =
ωcT
1 − z−1exp(−ωcT)
(2)
where T is the sampling time. Taking the inverse z transfor-
mation of Equation 2, we achieve the time domain difference
equation of the lowpass filter as
Filter out(n) =
RC× Charge out(n) + Filter out(n − 1) × e−
The corresponding SRE is expressed as:
T
T
RC (3)
Filter_out(n) = IF{true,
(T
RC)×Charge_out(n)+Filter_out(n-1)×e(−
The SRE is the difference equation of the lowpass filter.
T
RC),0}
Voltage Controlled Oscillator
The voltage controlled oscillator (VCO) is the key component
of the PLL system. It is used to generate a periodic signal,
which has the frequency proportional to the control input
voltage. The mathematical model of VCO can be expressed
as [3]:
V COout(t) = Accos(ωrt + KV CO
?t
0
u(τ)dτ + φ0)
(4)
where ωr is the VCO operating frequency, KV CO is the
VCO gain factor, u(t) is the control voltage coming from
the lowpass filter, and φ0 is the initial phase. In order to
convert voltage input to output frequency, the integral takes
place within the total phase. The SRE model of VCO is given
by
VCO_gain(n)=T×Filter_out(n)+VCO_gain(n-1),
VCO_out(n)=cos{ω0nT+KV CO×VCO_gain(n)+φ(n)},
VCO(n)=IF{VCO_out(n)≥0, 1, 0)}
where Filter out is the output of the analog filter, VCO out
is sinusoidal and VCO out div1 is square in shape. The first
SRE achieves the integral part of Equation 4. The second one
generates the continuous output of the VCO. The last one
acts as a comparator to generate the square signal with the
same frequency as V CO out.
Divider
The divider block works as frequency divider. In order to
achieve half frequency, the rising edge of the output occurs
every two periods of the input signal. In other words, the
output signal alternates at each rising edge of the input signal.
When the frequency select signal freq sel is activated, the
output of the divider holds the frequency as half as the input
signal. The entire functionality of the divider is modeled
using SRE as:
VCO_div(n+1)=IF{(VCO(n)=1)∧
(VCO(n-1)=0), ¬VCO_div(n), VCO_div(n)}
VCO_pfd(n+1)=IF{freq_sel(n)=1,
VCO_div(n), VCO(n)}
The first SRE performs the frequency divider function by
identifying the rising edge of the input signal. Once the rising
edge occurs, the output alternates itself. Otherwise, it retains
its previous value. The second SRE selects the V CO pfd
signal for the comparator.
V. PLL RUNTIME VERIFICATION
We simulated the PLL design shown in Figure 4 using the
C-SRE simulator framework described in Section III-B. The
simulation parameters are given in Table I. Several properties
were verified using the proposed methodology. In following,
we describe three example properties.
TABLE I
PLL PARAMETERS
Parameters
T(sec)
RC(sec)
α
Vc(V)
ω0(rad·Hz)
K0(rad·Hz·V−1)
New DC Level(V)
Value
10−8
0.0001
exp(-T/RC)
5
2π × 106
2ω0/V c
2.5
Description
Sampling time
Filter RC parameter
Charge time parameter
Voltage supply
Input signal frequency
VCO gain
Filter output
Property 1. Consider the PLL in Figure 4, the lock time is
one of the most important properties. It determines how fast
the frequency synthesizer gets stable from one frequency to
another. No useful data can be transmitted during this time. A
large lock time can reduce the data rate of the system. This
is the key factor when designing PLL circuits. The lock time