Conference Proceeding

New design method of low power over current protection circuit for low dropout regulator

Univ. of Electro-Commun., Chofu, Japan
05/2009; DOI:10.1109/VDAT.2009.5158092 pp.47 - 51 In proceeding of: VLSI Design, Automation and Test, 2009. VLSI-DAT '09. International Symposium on
Source: IEEE Xplore

ABSTRACT In this paper, a low power current protection circuit implemented in LDOs is presented. The proposed circuit, designed in 0.35 mum CMOS process, provides a precise limiting current as well as holding current with low dependency on both supply voltage and regulator output voltage. The experimental results showed the proposed circuit is operable in the regulator output voltage range VOUT = 1.2 V to VOUT = 3.6 V and supply voltage range VDD = VOUT + 0.5 V to VDD = 5.6 V . Since the proposed circuit is composed of few simple basic circuits such as comparator, Schmitt trigger, it has a low current consumption which is less than ISS = 0.82 muA at load current ILOAD = 200 mA. This makes the circuit suitable for low power and low voltage LDO design.

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Keywords

0.35 mum CMOS process
 
circuit suitable
 
ISS
 
low current consumption
 
low dependency
 
low power
 
low power current protection circuit
 
low voltage LDO design
 
proposed circuit
 
regulator output voltage
 
regulator output voltage range V<sub>OUT</sub>
 
Schmitt
 
simple basic circuits
 
supply voltage range VDD
 
VDD
 

S. Heng