All-Digital Ring-Oscillator-Based Macro for Sensing Dynamic Supply Noise Waveform

Abstract

This paper proposes an all-digital measurement circuit called a ldquogated oscillatorrdquo to capture the waveforms of dynamic power supply noise. An improved gated oscillator with a power-gating structure is also proposed. The gated oscillator is constructed using standard cells, and thus is easily embedded in SoCs. Its performance was evaluated using test chips fabricated in a 90 nm process. The gated oscillator achieved 5.3-5.9 Gsample/s with an area of 10.08 times 6.72 mum², and the improved power gating structure achieved 6.6-8.3 Gsample/s in a 90 nm process. The characteristics of the gated oscillator and related design issues are also discussed. These characteristics were verified on silicon. We evaluated the effect of the decoupling capacitance based on measurement results obtained using the gated oscillator, and demonstrated that it could be used to verify power integrity.

Full text

Page 1

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 6, JUNE 20091745
All-Digital Ring-Oscillator-Based Macro for Sensing
Dynamic Supply Noise Waveform
Yasuhiro Ogasahara, Masanori Hashimoto, Member, IEEE, and Takao Onoye, Senior Member, IEEE
Abstract—This paper proposes an all-digital measurement cir-
cuit called a “gated oscillator” to capture the waveforms of dy-
namic power supply noise. An improved gated oscillator with a
power-gating structure is also proposed. The gated oscillator is
constructed using standard cells, and thus is easily embedded in
SoCs. Its performance was evaluated using test chips fabricated in
a 90 nm process. The gated oscillator achieved 5.3–5.9 Gsample/s
with an area of 10.08
6.72m?, and the improved power gating
structureachieved6.6–8.3Gsample/sina90nmprocess.Thechar-
acteristics of the gated oscillator and related design issues are also
discussed. These characteristics were verified on silicon. We eval-
uated the effect of the decoupling capacitance based on measure-
ment results obtained using the gated oscillator, and demonstrated
that it could be used to verify power integrity.
Index Terms—Decoupling capacitance, measurement circuit,
power supply noise, ring oscillator.
I. INTRODUCTION
P
creasedcurrentconsumption.Decouplingcapacitancemitigates
dynamic power supply fluctuations [1]–[4]. However, excessive
decoupling capacitance consisting of MOS transistors results in
severe gate leakage in advanced technologies[2], [5]. Though
ensuring that adequate power supply wire also reduces power
supplynoise,wireresourcesarelimitedandexcessiveamountof
power supply wire makes signal routing difficult. There are sev-
eral studies on optimizing power distribution networks [6]–[12]
based on simulation. However, these capacitance insertion and
wire optimization methods are needed to be verified on silicon
in terms of their noise suppression efficiency.
For this purpose, a small measurement circuit suitable for
embedding in a device-under-test (DUT) is required to eval-
uate noise distribution within a chip. The simplicity of circuit
and layout design is another important factor in probing various
OWER supply noise has become a serious problem in re-
cent processes because of lower supply voltage and in-
Manuscript received March 26, 2008; revised January 31, 2009. Current ver-
sion published May 22, 2009. This work was supported in part by the Industrial
Technology Research Grant Program in 2006 of the New Energy and Indus-
trial Technology Development Organization (NEDO), Japan. The VLSI chip
in this study was fabricated through the chip fabrication program of the VLSI
Design and Education Center (VDEC), the University of Tokyo, in collabo-
ration with STARC, Fujitsu Limited, Matsushita Electric Industrial Company
Limited., NEC Electronics Corporation, Renesas Technology Corporation, and
Toshiba Corporation.
Y. Ogasahara is with Renesas Technology Corporation, Itami, Hyogo 664-
0005, Japan (e-mail: yasuhiro.ogasahara@gmail.com).
M.HashimotoandT.OnoyearewiththeDepartmentofInformationSystems
Engineering, Osaka University, Osaka 565-0871, Japan (e-mail: hasimoto@ist.
osaka-u.ac.jp; onoye@ist.osaka-u.ac.jp).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2009.2020192
points of interest inside a chip. Existing measurement circuits
[4], [13]–[23] use analog circuit techniques and need dedicated
analog power and bias lines. The additional routing and area
costs restrict the number of measurement circuits that can be in-
tegrated in a DUT and their allocatable positions. An ordinary
ring oscillator measurement [24], which is easy to implement,
observes the averaged supply voltage, not dynamic noise wave-
forms.Theringoscillatorthusacquireslimitedinformation,and
it cannot be used, for example, to evaluate the effects of decou-
pling capacitance.
In this paper, we propose an all-digital measurement circuit
for dynamic noise waveforms, whose basic structure is de-
scribed in our preliminary report [25], [26], and describe the
validation of the operation of the proposed circuit on test chips.
We also introduce an improved structure of the proposed circuit
using power gating. In a previous report [22], a circuit for
measuring dynamic noise waveforms using only digital circuit
components was proposed. However, a limitation of this circuit
is that the measurement system including the measurement
circuit and a DUT has to synchronize with the clock generated
inside the measurement circuit, and an external clock signal,
which is often given from a phase-locked loop (PLL) or the
outside of the chip, cannot be given to the DUT. As a result,
the operation of the DUT is not freely changeable, and the flex-
ibility of the measurement in terms of speed and intermittent
operation is highly limited. On the other hand, when using the
proposedcircuit, anyexternalclock canbesupplied totheDUT,
becausetheproposed circuit canoperate synchronizingwiththe
clock of the DUT. Our circuit has the following features: 1) it
consists of only digital standard cells; 2) it does not require a
dedicated analog power supply and reference voltage; 3) it has
a small circuit area; and 4) it operates with any external clock.
These features are made possible by a new idea: the proposed
circuit holds the ring oscillator state, whereas conventional cir-
cuits sample and hold the analog voltage[4], [14]. The proposed
measurement circuit is very easy to implement because there is
no need for the design techniques for analog circuits or for ded-
icated power lines for the measurement circuit. Our circuit can
be built only using standard cells. Its layout design is compat-
ible with common cell-based designs that use automatic place-
ment and routing tools, and its size and shape are flexible. The
operation clock of the DUT can be freely altered because our
measurement circuit can synchronize with any reference clock
given to the DUT.
Wealsodiscussthecharacteristicsoftheproposedcircuitand
methods of improving its performance. The performance of the
proposed circuit can be degraded by large slew of the transmis-
sion gate signal, unexpected charge accumulation, any kind of
injection locking, and discharge of leakage current. We discuss
0018-9200/$25.00 © 2009 IEEE
Authorized licensed use limited to: Masanori Hashimoto. Downloaded on May 31, 2009 at 18:23 from IEEE Xplore. Restrictions apply.

Page 2

1746IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 6, JUNE 2009
Fig. 1. Gated oscillator.
the design features considering these characteristics The mea-
surement results verified these characteristics and the improve-
ment in performance.
In Section II, we explain the proposed measurement circuit.
Section III describes the implementation of the test chips for
evaluationoftheproposedcircuit.SectionIVdescribestheeval-
uation of the proposed circuit on silicon, and Section V presents
a case study on evaluating decoupling capacitance design using
the proposed circuit. Section VI concludes this paper.
II. PROPOSED CIRCUIT
This section describes the proposed measurement circuit for
observing dynamic power supply noise. We also discuss the
characteristics and performance improvement of the proposed
circuit.
A. Basic Operation of the Proposed Circuit
Fig. 1 shows the proposed measurement circuit called a
“gated oscillator,” where the name derives from “gating” the
ring oscillator by the transmission gates. The gated oscillator
consists of only digital circuit components: inverters, a NAND
gate, and transmission gates. The layout design of the trans-
mission gate is simple, and the gated oscillator can basically
be constructed using only standard cells though standard cell
libraries do not necessarily include transmission gates.
The gated oscillator can observe dynamic waveforms of
power supply noise. The operation of the gated oscillator is
illustrated in Fig. 2. An ordinary ring oscillator can observe
power supply voltage as a toggle count or frequency. However,
it operates continuously and then measures only the average
voltage over a long time period. Our new idea is introducing a
state-keeping function to a ring oscillator. The gated oscillator
operates only while ‘enable’
is stopped by the transmission gates when ‘enable’
nonideality of the state preservation due to undesirable charge
accumulation will be discussed in Section II-B. Suppose a
power supply noise waveform in Fig. 2. The cycle count of the
oscillator depends on only the power supply voltage while en-
abled. The supply waveform while ‘enable’=1 is sampled, and
the operation of the gated oscillator is hold while ‘enable’=0.
As a result, the analog voltage of the power supply noise at a
specific timing is translated into a toggle count. To obtain a
high enough toggle count for accurate measurement, the gated
oscillator must be enabled repeatedly at the same timing. The
, and the oscillating operation
. A
Fig. 2. Operation of gated oscillator.
Fig. 3. Waveform measurement with gated oscillator.
repeated input of the same waveform is required as well as
conventional sampling oscilloscopes.
We aquire the waveform from obtained toggle counts as
shown in Fig. 3. The measured voltage is computed from the
toggle count measured by the counter and the prepared calibra-
tion table. The calibration table describes the relation between
the voltage and the toggle count, and is constructed beforehand
by measuring the toggle count without any noise varying the
voltage supplied to the proposed circuit. We repeatedly sweep
the sampling timing using the timing generator, measure the
count, and translate the count into voltage. The waveform
is reproduced from the measured voltages at each timing as
shown in Fig. 3. The measured voltage is the average voltage
of the actual waveform during each time slot, and hence the
bandwidth depends on the width of time slot in measurement.
Thegatedoscillatorrequiresasimpledigitalcounter,whereas
conventional circuits need analog input/output or an analog-to-
digital/digital-to-analog converter. In addition, common digital
timing generators, which are often used in other sampling cir-
cuits, such as [14], [22], can be adopted for the timing generator
of this circuit. Thus, the proposed measurement system can be
easily embedded by using only digital standard cells.
The gated oscillator can be used to capture three waveforms;
waveform, waveform, and
the gated oscillator shares
and
the
– waveform, that is the voltage amplitude between
and . On the other hand, when sharing
the gated oscillator measures
–
with the DUT, it senses
waveform. When
only,
waveform.
Authorized licensed use limited to: Masanori Hashimoto. Downloaded on May 31, 2009 at 18:23 from IEEE Xplore. Restrictions apply.

Page 3

OGASAHARA et al.: ALL-DIGITAL RING-OSCILLATOR-BASED MACRO FOR SENSING DYNAMIC SUPPLY NOISE WAVEFORM1747
Fig. 4. Intermediate voltage preservation of gated oscillator.
Fig. 5. Latch oscillator.
So far, for simplicity, the operation is explained supposing
thatthe clockgiventotheDUT isalso input tothetiming gener-
ator.However,thegatedoscillatorcanworkevenifthemeasure-
ment timing is interleaved. Suppose that the same noise wave-
form is repeated every 10 clock cycles of the DUT as a simple
example. In this case, by giving the clock divided by 10 to the
gated oscillator, we can observe the noise waveform.
1) Intermediate Voltage Preservation and Power Gating
Structure: An important metric of the measurement circuit is
the voltage resolution. In the gated oscillator, the number of
transmitting gates while ‘enable’
the supply voltage.
In addition, our gated oscillator can preserve the intermediate
voltage as shown in Fig. 4. When ‘enable’ is set from 1 to 0,
charging or discharging next stage gate is stopped, and the gate
input voltage is preserved at an intermediate level. After ‘en-
able’ is restored to 1, the transition restarts from the preserved
intermediate level.
This intermediate voltage preservation improves the voltage
resolution.Hereweevaluatetheimprovementbycircuitsimula-
tion.Weusethegatedoscillatorandthe“latchoscillator”shown
inFig.5.Thelatchoscillatorhasfeedbackloopsateachstage.In
this structure, intermediate voltage preservation is disabled, and
numberofgatetransmissionwhileenable
integer value. Fig. 6 shows the simulated voltage resolution of
two oscillators. TheX-axis shows thestable supplyvoltage, and
theY-axisshowsthetogglecountofthegatedoscillatornormal-
ized by the count at 1.0 V. The period and number of ‘enable’
are 300 ps and 250, respectively. The count increases lin-
early. Fig. 6 show that the toggle count of the oscillator is finely
proportional to supply voltage, and as shown in Fig. 6 the gated
changes depending on
‘1’isroundedtoan
Fig. 6. Calibration table for gated and latch oscillators in simulation.
Fig. 7. Gated oscillator with power gating structure.
oscillator is more sensitive to supply voltage than the latch os-
cillator. Thus, the intermediate voltage preservation improves
the voltage resolution.
From the viewpoint of voltage preservation, we also propose
an improved gated oscillator with a power gating structure as
shown in Fig. 7. Two transistors for power gating are added
for every inverter. The nMOS and pMOS for power gating
are controlled by ‘enable’ signal for the transmission gates.
This structure is more effective for voltage preservation, be-
cause charge sharing, which will be explained below, can be
mitigated. Placing the customized inverter cells is as easy as
placing standard cells though a custom layout is required for
the inverter cells. The performance improvement provided by
the power gating structure is discussed in detail in the next
subsection.
2) Bandwidth: The bandwidth of the gated oscillator de-
pends on the width of the ‘enable’ signal when the number of
sampling points can be increased. This is because the average
voltage is observed during the enable pulse. Here, we simu-
lated the measurement operation of the gated oscillator using
a sine waveform. Fig. 8 shows a simulation result of the mea-
surement operation. The width of ‘enable’ was set to 200 ps. A
2 GHz sine waveform was fed to a gated oscillator, as shown in
Fig. 8. Sampling with an ‘enable’ width of 200 ps was repeated
every 50 ps. The gated oscillator finely observed the given sine
Authorized licensed use limited to: Masanori Hashimoto. Downloaded on May 31, 2009 at 18:23 from IEEE Xplore. Restrictions apply.

Page 4

1748 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 6, JUNE 2009
Fig. 8. Simulation result of measuring sine waveform with gated oscillator.
Frequency of sine waveform was 2 GHz and ‘enable’ width was 200 ps.
waveform. In contrast, the measured waveform was attenuated
when a high frequency sine waveform was observed. This is be-
cause the gated oscillator observes the average voltage while
‘enable’ signal is asserted. Sine waveforms of 1, 2, 2.5, and
3.3 GHzwere measured.Theamplitudes of themeasuredwave-
forms were
0.25,1.01, 1.81, and
If the acceptable amplitude is
3 dB, the bandwidth in this case
isabout3GHz.Toimprovethebandwidth,thewidthof‘enable’
pulse must be shortened to reduce the averaging effect.
4.03 dB, respectively.
B. Characteristics and Design Issues
The most fundamental factor limiting the performance of the
gated oscillator is the performance of the nMOS and pMOS
transistors because the proposed gated oscillator consists of
CMOS inverters and transmission gates. A gated oscillator with
a faster transistor could achieve a higher sampling rate. When
the manufacturing technology advances and gate switching
becomes faster, it should be possible to operate using a shorter
‘enable’ pulse. Thus, the sampling rate and bandwidth of
the proposed gated oscillator will improve as the technology
advances.
The following three factors are also important in the perfor-
mance of the gated oscillator:
(1) the transition time of the ‘enable’ signal;
(2) undesirable charge accumulation (charge injection and
charge sharing);
(3) leakage in transmission gates.
The transmission gates stop and release the gated oscillator,
and faster switching of the transmission gates would improve
the performance of the gated oscillator. Thus, faster ‘enable’
transition of the transmission gate is desirable. Fig. 9 shows the
simulated voltage resolution of the gated oscillator, when dif-
ferent slews of the ‘enable’ signal are given. The curve with
a slow slew (50 ps) shows a lower voltage resolution than the
curve with an ideal slew (0.01 ps). The slew of the ‘enable’
signal can be shortened by using a large driver, and also smaller
gates for the gated oscillator.
When transmission gates are set ON or OFF, there exist un-
desirable charge accumulation which we do not expect. These
effects can degrade the performance of the gated oscillator.
Causes for the undesirable charge accumulation are charge
injection and charge sharing.
Fig.9. Performanceoftransmissiongatelimitsperformanceofgatedoscillator
(simulation).
Fig. 10. Charge sharing.
First we refer to charge injection. When the transmission
gates are set to OFF, the gate input voltage is preserved at an
intermediate level. However, charge injection causes variation
in the preserved voltage and adversely affects the perfor-
mance of the gated oscillator. Charge injection is normally
alleviated by balancing the size ratio of the pMOS and nMOS
of the transmission gates. However, this method does not
necessarily improve the signal-propagation performance of
the transmission gate, and may lower the performance of the
gated oscillator. As smaller transmission gate injects a smaller
charge, in our experiments, simply using smaller transmission
gates reduced charge injection.
Charge sharing is explained in Fig. 10. While the transmis-
sion gates are OFF, charging node n1 is stopped and the voltage
ofn1 ispreserved.However,node n2has parasitic capacitances,
and the transmission gates cannot stop charging node n2. When
the transmission gates are set to ON, the charge in node n2 is in-
jected to node n1, and the preserved voltage fluctuates. A gated
oscillator with a power-gating inverter, which was described in
the previous section in Fig. 11, alleviates charge sharing. Power
gating prevents the parasitic capacitance from being charged, as
shown in Fig. 11, and improves the waveform acquisition per-
formance.
Here we demonstrate the effect of two approaches mentioned
above; using smaller transmission gates and the power gating
structure. The simulation results for voltage resolution are
shown in Fig. 12. Ideal repetitive pulses with 100 ps width were
used as the ‘enable’ signal, and toggle counts were observed
with a supply voltage from 0.6 to 1.1 V, increasing in 5 mV
steps. The count of the gated oscillator basically increased
monotonically as the supply voltage increased. However, there
Authorized licensed use limited to: Masanori Hashimoto. Downloaded on May 31, 2009 at 18:23 from IEEE Xplore. Restrictions apply.

Page 5

OGASAHARA et al.: ALL-DIGITAL RING-OSCILLATOR-BASED MACRO FOR SENSING DYNAMIC SUPPLY NOISE WAVEFORM1749
Fig. 11. Proposed power gating structure for gated oscillator.
Fig.12. Comparisonofsupplyvoltagevs.#togglesinsimulation.Circuitstruc-
tures differed and ‘enable’ was 100 ps wide.
were several voltage ranges where counts did not change. In
this paper, we call this range the “insensitive voltage range.”
The small (0.5X size) transmission gate and power-gating
inverter reduced the insensitive voltage range and improved the
voltage resolution due to less charge injection and less charge
sharing, respectively.
The insensitive voltage ranges are found at the same counts
instructureswith1Xand 0.5Xtransmissiongates.Forexample,
both structures have insensitive voltage ranges at counts of 680
and 907 in Fig. 12. In these cases, the enable widths are integral
multiplesofthestagedelayofthegatedoscillator,andtheinsen-
sitive voltage ranges imply a kind of injection locking. In fact,
680 and 907 counts correspond to 25 ps and 33 ps gate delays
that are 1/4 and 1/3 of the ‘enable’ width. The gated oscillator
shows fine resolution at most voltage range other than insensi-
tive voltage range. This range can be shifted by changing the
configuration, i.e., the gate sizes, and sub-10-mV resolution can
be achieved by implementing two differently configured gated
oscillators.
When the transmission gates have a long OFF period, dis-
charge due to leakage can also adversely affect the measure-
ment results with the gated oscillator. The preserved interme-
diate voltage is not perfectly held because of the subthreshold
leakage current in the transmission gate and the gate leakage
current of the inverter. For example, supposing that the gate
input capacitance and leakage current are 5 fF and 5 nA, re-
spectively, for simplicity, and the preserved voltage is varied by
100 mVaftera100nsholdingperiod.Toolongaholdingperiod
causes notonlyvariationinthepreservedvoltage,butalsofunc-
tional failure. As mentioned in Section II-A, the gated oscillator
works even when the measurement timing is interleaved. On
the other hand, some design efforts might be required when the
holding period would be long in a target measurement. In this
case, transistors with low leakage current (e.g., high threshold
Fig. 13. Micrographs of two test chips.
voltage transistor) are likely to be selected for the transmission
gates. Even if a low-leakage transistor is not available or not ef-
fective enough, the latch oscillator still works because its feed-
back structure maintains the condition of the oscillator.
III. IMPLEMENTATION OF TEST CHIPS
We fabricated two test chips using a 90 nm CMOS process.
The nominal supply voltage of this process was 1.0 V. Fig. 13
shows micrographs of the test chips, which were 2.5
in size. Each test chip included several TEGs, a PLL, and shift
registers. The shift registers were written and read by external
input and output. The control signals for the TEGs and PLL
were stored in the shift registers. A part of the shift register
also operated as a counter, and counted the toggles of the gated
oscillator.
Each TEG included a DUT and a measurement circuit. The
measurement circuit consisted of the gated oscillator and cir-
cuits for ‘enable’ signal generation. The external clock signal
is input to DUTs as an operating clock. ‘enable’ signal is gen-
erated with given clock because ‘enable’ pulse needs to syn-
chronizes with the given clock to observe waveform at the same
timing repeatedly. Fig. 14 shows our ‘enable’ signal generator,
whichconsistsofvariabledelays,anXORgate,ANDgates,and
a multiplexer. This generator varies the pulse width and timing
of the ‘enable’ signal by controlling the variable-delay circuits.
The generated pulse width is
the delays in the variable-delay circuits. The pulse timing of
‘enable’ from ‘CLK’ edge is changed from
. The reference edge of ‘CLK’ is chosen from
the rise and fall transition by the ‘sel’ signal. In this work, we
used the variable delay circuit shown in Fig. 15, which consists
2.5 mm
, where, are
to
Authorized licensed use limited to: Masanori Hashimoto. Downloaded on May 31, 2009 at 18:23 from IEEE Xplore. Restrictions apply.