A 110nm RFCMOS GPS SoC with 34mW −165dBm tracking sensitivity
ABSTRACT A low-power and high-performance RFCMOS SoC GPS receiver is introduced in this paper. It is fabricated in a 0.11 mum process with 6.2times6.2mmz TFBGA package. The power consumption is 34 mW during tracking stage and 45 mW during acquisition stage. The tracking sensitivity is up to -165 dBm with the most competitive TTFF performance. This GPS receiver is designed for PND/GSM/CDMA handsets and is compatible with various reference clock frequencies from 12.6 MHz to 40 MHz. It is a highly integrated solution with intelligent power management scheme and minimum external components. The RF performance is not affected by digital activities due to well-designed isolation schemes. The RF and system performance comparison and the chip micrograph is also illustrated.
Conference Proceeding: A GPS/Galileo SoC with adaptive in-band blocker cancellation in 65nm CMOS[show abstract] [hide abstract]
ABSTRACT: The proliferation of location-based applications inside various handheld electronic devices, such as mobile phones and internet tablets, demands the GPS system to have low power consumption, small form-factor and be co-located on the same device with other radio systems, such as cellular, BT, and WLAN. The conventional GPS solution often uses two SAW filters, before and after an external LNA, to meet the requirements of low noise and multi-radio coexistence. Nevertheless, it is highly desirable to remove the external LNA and interstage SAW filter due to size and cost, which presents a great design challenge to achieve high out-of-band linearity with very low power consumption. To fulfill these stringent requirements, a more comprehensive approach is needed to tar get a radio architecture with a proper RX system budgeting and optimal circuit design. In addition, a GPS system can be desensitized by unexpected in-band blockers generated from other subsystems on the same platform, such as LCD display, PMU, CPU system clocks, etc. The GPS digital baseband processor must possess the capability to withstand in-band blockers without significant performance degradation. This paper presents a GPS/Galileo SoC with an adaptive in-band blocker cancellation scheme, which is implemented in a 65nm CMOS process.Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International; 03/2011