A 110nm RFCMOS GPS SoC with 34mW −165dBm tracking sensitivity
ABSTRACT A low-power and high-performance RFCMOS SoC GPS receiver is introduced in this paper. It is fabricated in a 0.11 mum process with 6.2times6.2mmz TFBGA package. The power consumption is 34 mW during tracking stage and 45 mW during acquisition stage. The tracking sensitivity is up to -165 dBm with the most competitive TTFF performance. This GPS receiver is designed for PND/GSM/CDMA handsets and is compatible with various reference clock frequencies from 12.6 MHz to 40 MHz. It is a highly integrated solution with intelligent power management scheme and minimum external components. The RF performance is not affected by digital activities due to well-designed isolation schemes. The RF and system performance comparison and the chip micrograph is also illustrated.
- Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International; 01/2013
- Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International; 03/2011
Conference Paper: A Low Power Asynchronous GPS Baseband ProcessorAsynchronous Circuits and Systems (ASYNC), 2012 18th IEEE International Symposium on; 01/2012