Conference Proceeding

A 110nm RFCMOS GPS SoC with 34mW −165dBm tracking sensitivity

03/2009; DOI:10.1109/ISSCC.2009.4977404 pp.254 - 255,255a In proceeding of: Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International
Source: IEEE Xplore

ABSTRACT A low-power and high-performance RFCMOS SoC GPS receiver is introduced in this paper. It is fabricated in a 0.11 mum process with 6.2times6.2mmz TFBGA package. The power consumption is 34 mW during tracking stage and 45 mW during acquisition stage. The tracking sensitivity is up to -165 dBm with the most competitive TTFF performance. This GPS receiver is designed for PND/GSM/CDMA handsets and is compatible with various reference clock frequencies from 12.6 MHz to 40 MHz. It is a highly integrated solution with intelligent power management scheme and minimum external components. The RF performance is not affected by digital activities due to well-designed isolation schemes. The RF and system performance comparison and the chip micrograph is also illustrated.

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Keywords

6.2times6.2mmz TFBGA package
 
acquisition stage
 
compatible
 
competitive TTFF performance
 
high-performance RFCMOS SoC GPS receiver
 
intelligent power management scheme
 
minimum external components
 
PND/GSM/CDMA handsets
 
RF
 
RF performance
 
system performance comparison
 
various reference clock frequencies