Conference Paper

# A 400-to-900 MHz receiver with dual-domain harmonic rejection exploiting adaptive interference cancellation

Univ. of Twente, Enschede, Netherlands

DOI: 10.1109/ISSCC.2009.4977393 Conference: Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International Source: IEEE Xplore

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**ABSTRACT:**In this paper, harmonic rejection (HR) mixing techniques to obtain a high level of HR are described. This is achieved by reducing the sensitivity to mismatches in devices operating at high frequencies. A design fabricated in a 110-nm CMOS process rejects up to the first 14 local oscillator (LO) harmonics and achieves third, fifth, and seventh HR ratios in excess of 52, 54, and 55 dB, respectively, without any calibration or trimming. This mixer also rejects flicker noise and has improved quadrature matching and IIP2 performance. By using a clock N times the desired LO frequency, this scheme rejects the (N-1)th LO harmonic only by an amount of 20log(N-1) dB. A new technique is presented that enables better HR for the (N-1)th harmonic while preserving the level of rejection for other harmonics. This mixer fabricated in a 55-nm standard CMOS process has a programmable number of 8, 10, 12, or 14 mixer phases and achieves an improvement of 29 dB for the (N-1)th harmonic while achieving 52 dB of rejection for the third harmonic. It also rejects flicker noise and has an IIP2 performance of 68 dBm.IEEE Journal of Solid-State Circuits 08/2013; 48(8):1862-1874. · 3.06 Impact Factor - [Show abstract] [Hide abstract]

**ABSTRACT:**The local oscillator harmonics corrupt the desired signal in broadband RF receivers by downconverting interferers. This paper proposes the notion of harmonic rejection in the front-end low-noise amplifier so as to relax the stringent matching required of harmonic-reject mixers. Described are frequency response shaping techniques by feedforward and unilateral Miller capacitance multiplication for a signal bandwidth of 100 MHz to 10 GHz. A calibration algorithm is also proposed for the tuning of the frequency response. An experimental prototype fabricated in 65-nm digital CMOS technology provides at least 20 dB of rejection while consuming 8.64 mW with a 1.2-V supply.IEEE Journal of Solid-State Circuits 01/2013; 48(4):1072-1084. · 3.06 Impact Factor - [Show abstract] [Hide abstract]

**ABSTRACT:**A wideband direct-conversion receiver front-end featuring a new harmonic rejection technique is demonstrated in 65-nm CMOS. The circuit consists of a two-stage low-noise amplifier, the first stage with capacitive feedback, a harmonic rejection mixer using 25% and 50% duty cycle local oscillator signals, and a third-order channel-select filter with configurable bandwidth. The receiver front-end is intended for surface-acoustic-wave-less cellular applications, and its performance was measured at 900- and 1800-MHz bands. The average harmonic rejection over GSM and LTE channel bandwidths is between 60 and 70 dB. Peak harmonic rejection exceeds 80 dB. The noise figures (NFs) are 3.3 and 3.9 dB for the complete receiver front-end in low band and high band, respectively, with an S11 below -15 dB from 500 MHz to 2.5 GHz. The 1-dB received signal compression points with a blocker present at 20/80 MHz offset for low/high band are 0 and +2 dBm, respectively. The NF with 0-dBm blocker is 13 dB. For low band, the in-band IIP3 and IIP2 are -14.8 and > 49 dBm, respectively, and, for high band, -18.2 and > 44 dBm. The circuit worst case consumes 80 mW of power.Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2013; 60(5):242-246. · 1.33 Impact Factor

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