Conference Paper

A 400-to-900 MHz receiver with dual-domain harmonic rejection exploiting adaptive interference cancellation

Univ. of Twente, Enschede, Netherlands
DOI: 10.1109/ISSCC.2009.4977393 In proceeding of: Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International
Source: IEEE Xplore

ABSTRACT Wideband direct-conversion harmonic-rejection (HR) receivers for software- defined radio aim to remove or relax the pre-mixer RF filters, which are inflexible, bulky and costly. HR schemes are often used, but amplitude and phase mismatches limit HR to between 30 and 40 dB. A quick calculation shows that much more rejection is wanted: in order to bring harmonic responses down to the noise floor (e.g. -100 dBm in 10 MHz for 4 dB NF), and cope with interferers between -40 and 0 dBm, an HR of 60 to 100 dB is needed. Also in terrestrial TV receivers and in applications like DVB-H with co-existence requirements with GSM/WLAN transmitters in a small telephone, high HR is needed. In this work, an architecture aiming for >80 dB HR is shown. It consists of an analog front-end followed by adaptive interference cancellation (AIC) in the digital domain. AIC is known for its ability to adapt to and mitigate unknown system non-idealities, e.g. gain and phase imbalances. Due to its adaptivity it can achieve large improvements, provided the interference estimate is accurate. To the authors' knowledge, they are the first to explore AIC for HR and previously presented simulation results. Here a new and different architecture and measured results with the RF part implemented in 65 nm CMOS and the AIC in software are presented.

0 Bookmarks
 · 
119 Views
  • [Show abstract] [Hide abstract]
    ABSTRACT: A 48–885–MHz ultralow-cost high-performance mobile analog TV (MATV) tuner with an improved harmonic rejection design algorithm achieves 5.5 dB/4.5 dB noise figure at VHF and UHF bands, respectively, and adjacent channel interference (ACI) ${rm N}+1/{rm N}+2$ performance of 24/29 dB. A harmonic rejection mixer (HRM) with a tracking filter (TF) scheme employing three external inductors, one for each TV band, achieves better than 78/83-dB harmonic-rejection for the VHFI/VHFIII bands. A single LC-tank VCO with a programmable divider that has a 50% duty cycle correction scheme covers the entire TV band with accurate LO phases. A digital automatic gain control (AGC) scheme detects the presence of ACI and/or GSM burst-mode blockers through an RF wideband peak detector (WBPD) and adjusts the receiver gain for optimum dynamic range. The RF tuner is fabricated in 65-nm CMOS technology with silicon area of only 1.25 $hbox{mm}^{2}$ and draws 37/19 mA for analog TV and FM radio receiver modes, respectively.
    IEEE Journal of Solid-State Circuits 01/2013; 48(5):1174-1187. · 3.06 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: A wideband direct-conversion receiver front-end featuring a new harmonic rejection technique is demonstrated in 65-nm CMOS. The circuit consists of a two-stage low-noise amplifier, the first stage with capacitive feedback, a harmonic rejection mixer using 25% and 50% duty cycle local oscillator signals, and a third-order channel-select filter with configurable bandwidth. The receiver front-end is intended for surface-acoustic-wave-less cellular applications, and its performance was measured at 900- and 1800-MHz bands. The average harmonic rejection over GSM and LTE channel bandwidths is between 60 and 70 dB. Peak harmonic rejection exceeds 80 dB. The noise figures (NFs) are 3.3 and 3.9 dB for the complete receiver front-end in low band and high band, respectively, with an S11 below -15 dB from 500 MHz to 2.5 GHz. The 1-dB received signal compression points with a blocker present at 20/80 MHz offset for low/high band are 0 and +2 dBm, respectively. The NF with 0-dBm blocker is 13 dB. For low band, the in-band IIP3 and IIP2 are -14.8 and > 49 dBm, respectively, and, for high band, -18.2 and > 44 dBm. The circuit worst case consumes 80 mW of power.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2013; 60(5):242-246. · 1.33 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: A surface acoustic wave-less receiver front-end for GSM, TD-LTE and TD-SCDMA standards featuring a novel low noise amplifier (LNA) architecture and harmonic rejection technique is presented. The two-stage LNA uses capacitive feedback in the first stage for wideband input matching. It can operate from 500 MHz up to 2.5 GHz with an S11 below −15 dB. The harmonic rejection mixer structure operates using two- and four-phase local oscillator signals and is capable of achieving a high harmonic rejection over a wide channel bandwidth. The average harmonic rejection is above 60 dB measured over a 20 MHz LTE channel and above 70 dB over a GSM channel. The mixer structure contains digitally tunable resistor and capacitor banks for precise tuning, causing the peak harmonic rejection in the channel to exceed 80 dB. The precise tuning capability ensures good harmonic rejection in the presence of process mismatch and duty cycle mismatch. The 1-dB received signal compression point with a blocker present at 20/80 MHz offset for low-/high-band is 0 and +2 dBm, respectively. In-band IIP3, and IIP2 are −14.8 and >49 dBm, respectively, for low-band. For high-band they are −18.2 and >44 dBm. Implemented in 65 nm CMOS, the complete front-end consumes 80 mW of power.
    Analog Integrated Circuits and Signal Processing 10/2013; · 0.55 Impact Factor

Full-text

View
0 Downloads
Available from