Conference Paper

# A 400-to-900 MHz receiver with dual-domain harmonic rejection exploiting adaptive interference cancellation

Univ. of Twente, Enschede, Netherlands

DOI: 10.1109/ISSCC.2009.4977393 Conference: Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International Source: IEEE Xplore

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**ABSTRACT:**A wideband direct-conversion receiver front-end featuring a new harmonic rejection technique is demonstrated in 65-nm CMOS. The circuit consists of a two-stage low-noise amplifier, the first stage with capacitive feedback, a harmonic rejection mixer using 25% and 50% duty cycle local oscillator signals, and a third-order channel-select filter with configurable bandwidth. The receiver front-end is intended for surface-acoustic-wave-less cellular applications, and its performance was measured at 900- and 1800-MHz bands. The average harmonic rejection over GSM and LTE channel bandwidths is between 60 and 70 dB. Peak harmonic rejection exceeds 80 dB. The noise figures (NFs) are 3.3 and 3.9 dB for the complete receiver front-end in low band and high band, respectively, with an S11 below -15 dB from 500 MHz to 2.5 GHz. The 1-dB received signal compression points with a blocker present at 20/80 MHz offset for low/high band are 0 and +2 dBm, respectively. The NF with 0-dBm blocker is 13 dB. For low band, the in-band IIP3 and IIP2 are -14.8 and > 49 dBm, respectively, and, for high band, -18.2 and > 44 dBm. The circuit worst case consumes 80 mW of power.Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2013; 60(5):242-246. · 1.19 Impact Factor - [Show abstract] [Hide abstract]

**ABSTRACT:**A wide-band harmonic rejection mixer for TV tuners with an improved design algorithm is fabricated in 65-nm CMOS process. A more realistic mathematical formula is derived to calculate harmonic rejection performance. The third and fifth order harmonic rejection ratio calculation, based on the new proposed equations, precisely predicts simulation results. A systematic design optimization technique pushes the mean of the harmonic rejection performance to a higher value resulting in better yield. The measured third and fifth order harmonic rejection ratio for 2000 samples is better than -56dBc for VHFI and II bands without increasing any circuit complexity or implementation difficulty.Radio Frequency Integrated Circuits Symposium (RFIC), 2012 IEEE; 01/2012 -
##### Conference Paper: Clock-gated harmonic rejection mixers

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**ABSTRACT:**In this paper, harmonic-rejection mixers (HRM) in which incoming radio frequency (RF) signal is multiplied by square-wave local-oscillator (LO) output, are described. Starting with the generalization of the conventional HRM concept, a technique to reject higher order harmonics, above the third and fifth, is presented. After a brief description of the conventional HRM and its limitations, an improved HRM that achieves a higher level of harmonic rejection (HR) for higher order harmonics as well, is described. By using a clock N times the desired LO frequency, this scheme rejects the (N-1)th LO harmonic only by an amount of 20log(N - 1) dB. A new technique is presented that achieves 19 dB better HR for the (N - 1)th harmonic while preserving the level of rejection for other harmonics. Mixer embodying this technique is fabricated in 55 nm standard CMOS process and measured results are discussed. Flicker noise cancellation and HR performance achieved are examined for this new topology. This mixer rejects the (N - 1)th harmonic in excess of 39 dB for N = 4 while achieving greater than 52 dB of rejection for other harmonics.Custom Integrated Circuits Conference (CICC), 2012 IEEE; 01/2012

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