Conference Paper

A 400-to-900 MHz receiver with dual-domain harmonic rejection exploiting adaptive interference cancellation

Univ. of Twente, Enschede, Netherlands
DOI: 10.1109/ISSCC.2009.4977393 Conference: Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International
Source: IEEE Xplore


Wideband direct-conversion harmonic-rejection (HR) receivers for software- defined radio aim to remove or relax the pre-mixer RF filters, which are inflexible, bulky and costly. HR schemes are often used, but amplitude and phase mismatches limit HR to between 30 and 40 dB. A quick calculation shows that much more rejection is wanted: in order to bring harmonic responses down to the noise floor (e.g. -100 dBm in 10 MHz for 4 dB NF), and cope with interferers between -40 and 0 dBm, an HR of 60 to 100 dB is needed. Also in terrestrial TV receivers and in applications like DVB-H with co-existence requirements with GSM/WLAN transmitters in a small telephone, high HR is needed. In this work, an architecture aiming for >80 dB HR is shown. It consists of an analog front-end followed by adaptive interference cancellation (AIC) in the digital domain. AIC is known for its ability to adapt to and mitigate unknown system non-idealities, e.g. gain and phase imbalances. Due to its adaptivity it can achieve large improvements, provided the interference estimate is accurate. To the authors' knowledge, they are the first to explore AIC for HR and previously presented simulation results. Here a new and different architecture and measured results with the RF part implemented in 65 nm CMOS and the AIC in software are presented.

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    • "However, to overcome the problem of LO harmonics with an HRM regarding digital TV requirements, HRM needs many sub-mixers and phase-shifted LOs that make HRM intricate and impossible (Shah, 2009). Over 60 dB rejection is obtained by employing a harmonic rejection stage for third and also fifth LO harmonics (Moseley et al., 2009). However, it makes the system complicated. "
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    ABSTRACT: To improve the linearity of the transconductor in digital TV tuner application, a new technique of multiple gated transistors in self-biasing basis is presented. The proposed design decreases the bill-of-material (BOM) and offers less complexity for the structure. In addition, the proposed transconductor with third-order Chebyshev introduces a low-pass filter with low power consumption and a cut-off frequency of 50–200 MHz. The hybrid tracking low-pass filter is designed to overcome the issue of local oscillator harmonic-mixing for the Advanced Television System Committee terrestrial digital TV tuner integrated circuit. The proposed operational transconductor amplifier (OTA) is designed and implemented in 90 nm complementary metal-oxide semiconductor technology. The simulation result with a two-tone test at 100 MHz centre frequency proves that the proposed OTA has 5 dBm input-referred third-order intercept point (IIP3) compared with a single-gate OTA in the third-order Chebyshev filter. The proposed OTA achieves the maximum noise figure (NF) of 13 dB and maximum IIP3 of approximately 21.7 dBm at 100 MHz, whereas consuming 18 mA with 1.2 V supply voltage it shows great improvement compared to recent research works.
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    • "By contrast, a radio targeting the range of 900 MHz to 5 GHz (cellular to WLAN bands) must deal with harmonics up to the fifth or sixth order. For this reason, such radios have focused on harmonic-reject mixers (HRMs) [14]–[16] derived from the original concept in [17]. Cognitive radios do not easily lend themselves to harmonic-reject mixing. "
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    ABSTRACT: Cognitive radios are expected to communicate across two or three frequency decades by continually sensing the spectrum and identifying available channels. This paper describes the issues related to the design of wideband signal paths and the decades-wide synthesis of carrier frequencies. A new CMOS low-noise amplifier topology for the range of 50 MHz to 10 GHz is introduced that achieves a noise figure of 2.9 to 5.7 dB with a power dissipation of 22 mW. Several multi-decade carrier generation techniques are proposed and a CMOS prototype is presented that exhibits a phase noise of -94 to -120 dBc/Hz at 1-MHz offset while consuming 31 mW.
    IEEE Journal of Solid-State Circuits 09/2010; 45(8-45):1542 - 1553. DOI:10.1109/JSSC.2010.2049790 · 3.01 Impact Factor
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    • "Both improve HR by rejecting harmonics in two successive steps ( " iterative " ), and both share the same 8-phase RF-to-baseband downconverter as a first HR stage. Compared to [17]–[19], we greatly extend the analysis and show additional experimental results. Compared to [20], this work derives the interference estimate in another way, presents measurements and achieves better performance due to the better interference estimate. "
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    ABSTRACT: A software-defined radio (SDR) receiver with improved robustness to out-of-band interference (OBI) is presented. Two main challenges are identified for an OBI-robust SDR receiver: out-of-band nonlinearity and harmonic mixing. Voltage gain at RF is avoided, and instead realized at baseband in combination with low-pass filtering to mitigate blockers and improve out-of-band IIP3. Two alternative ¿iterative¿ harmonic-rejection (HR) techniques are presented to achieve high HR robust to mismatch: a) an analog two-stage polyphase HR concept, which enhances the HR to more than 60 dB; b) a digital adaptive interference cancelling (AIC) technique, which can suppress one dominating harmonic by at least 80 dB. An accurate multiphase clock generator is presented for a mismatch-robust HR. A proof-of-concept receiver is implemented in 65 nm CMOS. Measurements show 34 dB gain, 4 dB NF, and + 3.5 dBm in-band IIP3 while the out-of-band IIP3 is +16 dBm without fine tuning. The measured RF bandwidth is up to 6 GHz and the 8-phase LO works up to 0.9 GHz (master clock up to 7.2 GHz). At 0.8 GHz LO, the analog two-stage polyphase HR achieves a second to sixth order HR > 60 dB over 40 chips, while the digital AIC technique achieves HR > 80 dB for the dominating harmonic. The total power consumption is 50 mA from a 1.2 V supply.
    IEEE Journal of Solid-State Circuits 01/2010; 44(12-44):3359 - 3375. DOI:10.1109/JSSC.2009.2032272 · 3.01 Impact Factor
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