Conference Proceeding

A low-power dual-clock strategy for digital circuits of EPC Gen2 RFID tag

Dept. of Electron. Sci. & Technol., Univ. of Sci. & Technol. of China, Hefei
05/2009; DOI:10.1109/RFID.2009.4911177 pp.7 - 14 In proceeding of: RFID, 2009 IEEE International Conference on
Source: IEEE Xplore

ABSTRACT Power consumption is critical to the performance of EPC Gen2 RFID tags. System clock frequency of tags should be as low as possible to reduce the power consumption and still conform to the protocol. This paper analyses the impact of different clock strategies on digital circuits of EPC Gen2 tag. An error shift approach is proposed to reduce the backscatter link frequency (BLF) errors. A dual-clock strategy with both 1.28 and 2.56 MHz clocks for the digital circuits is developed. Compared with the 1.92 MHz unitary-clock strategy, the dual-clock strategy offers larger decoding margins and BLF margins, consumes 5.66% to 9.44% less power estimated in CMOS 0.18 mum technologies, and fully conforms to the EPC Gen2 protocol as well.

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Keywords

backscatter link frequency
 
CMOS 0.18 mum technologies
 
different clock strategies
 
digital circuits
 
dual-clock strategy
 
EPC Gen2 RFID tags
 
error shift approach
 
larger decoding margins
 
MHz clocks
 
MHz unitary-clock strategy
 
paper analyses
 
power consumption
 
System clock frequency