An 8μW 100kS/s successive approximation ADC for biomedical applications
ABSTRACT A successive approximation analog-to-digital converter (SA-ADC) for biomedical application is presented. It is based on 0.18-mum standard CMOS technology and operates at low supply voltage at 1 V. Boosted switch for sample-and-hold stage, split capacitor array for DAC, and clocked rail-to-rail comparator are used to achieve low-power consumption. The ADC has signal-to-noise-and-distortion ratio of 53 dB for supply voltage of 1 V, at sampling rate of 100 kS/s and power consumption of 8 muW.
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ABSTRACT: This paper proposes an extendable front-end readout chip (EFRC) for electroencephalography (EEG) measurements. An EFRC is developed for EEG measurement with features including low power consumption, a high signal-to-noise ratio, and highly efficient chip area usage. A chopper-stabilized differential difference amplifier (CHDDA) is used in the first stage to amplify signals and then during another adjustable amplification stage and filter are used to process biomedical signals. A 10-bit successive approximation register analog-to-digital converter (SAR-ADC) then links to the back-end for digital signal processing. In the last stage, shift-register pairs are used to transmit data to the next chip and receive data from the previous chip. The shift register design allows the number of channels to be extended. A TSMC 0.18 um CMOS process is used to design the EFRC and it operates with a 1.8 V supply voltage. The results shows that the total power consumption for the EFRC chip is approximately 80.268 uW and the chip area is approximately 944 × 863 um2.Consumer Electronics (ICCE), 2013 IEEE International Conference on; 01/2013
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ABSTRACT: In this paper, a low power and low noise eight-channel analog front-end (AFE) IC for portable brain-heart monitoring applications is presented. The developed IC features a fully integrated eight-channel design which includes one channel for diffuse optical tomography (DOT), three channels for electrocardiography (ECG), and four channels for electroencephalography (EEG). In order to achieve the targets of lower power, lower noise, and more efficient area utilization, a new programmable readout channel is invented which is composed of a chopper-stabilized differential difference amplifier (CHDDA), an adjustable gain amplifier, and an adjustable low pass filter (LPF). Furthermore, a 10-bit successive approximation register analog-to-digital converter (SAR-ADC) is employed in conjunction with an analog multiplexer to select a particular biosignal for analog-to-digital conversion. The proposed IC has been fabricated in the TSMC 0.18 um CMOS technology and simulated using HSPICE under a 1.8-V supply voltage and an operating frequency of 512 Hz. The power supply rejection ratio (PSRR) +/- of the CHDDA is 113/105 dB. The power consumption of the programmable readout channel and the SAR-ADC is about 71.159 μW and 8.27 μW, respectively. The total power consumption of the full AFE chip is about 506.38 μW and the chip area is about 1733 × 1733 um<sup>2</sup>.Life Science Systems and Applications Workshop (LiSSA), 2011 IEEE/NIH; 05/2011