Article
Performance Enhancement in Double-Gated Poly-Si Nanowire Transistors With Reduced Nanowire Channel Thickness
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu
IEEE Electron Device Letters (impact factor:
2.85).
07/2009;
DOI:10.1109/LED.2009.2018493
pp.644 - 646
Source: IEEE Xplore
-
Citations (0)
- Cited In (1)
-
Article: Electrostatic Discharge Robustness of Si Nanowire Field-Effect Transistors
[show abstract] [hide abstract]
ABSTRACT: Electrostatic discharge (ESD) performance of N-type double-gated Si nanowire (NW) thin-film transistors is investigated, for the first time, using the transmission line pulsing technique. The ESD robustness of these devices depends on the NW dimension, number of channels, plasma treatment, and layout topology. The failure currents, leakage currents, and on-state resistances are characterized, and possible ESD protection applications of these devices for future NW field-effect-transistor-based integrated circuits are also discussed.IEEE Electron Device Letters 10/2009; · 2.85 Impact Factor
Data provided are for informational purposes only. Although carefully collected, accuracy cannot be guaranteed.
The impact factor represents a rough estimation of the journal's impact factor and does not reflect the actual
current impact factor.
Publisher conditions are provided by RoMEO. Differing provisions from the publisher's actual policy or licence
agreement may be applicable.
Keywords
conduction mechanism
device operation
dramatic performance enhancement
independent gates
new method
NW
NW channel
NW device
NW structure
polycrystalline silicon
rectangular-shaped NW channels
