Polarity dependent breakdown of the high-κ/SiOx gate stack: A phenomenological explanation by scanning tunneling microscopy

Applied Physics Letters (Impact Factor: 3.52). 06/2008; 92(19):192904 - 192904-3. DOI: 10.1063/1.2926655
Source: IEEE Xplore

ABSTRACT From scanning tunneling microscopy, we present unambiguous evidence of thermally induced localized conduction paths exhibiting an asymmetrical conduction property in the high- κ gate stack. The tunneling current under gate injection biasing is found to be much larger than that under substrate injection biasing after a 700 ° C postdeposition anneal, i.e., the localized paths exhibit a much lower resistance under gate injection biasing. This finding provides a phenomenological explanation for the polarity dependent breakdown of the high- κ gate stack as observed from electrical stressing of large-area metal-oxide-semiconductor capacitors.

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    ABSTRACT: The presence of grain boundaries (GBs) in polycrystalline high-κ (HK) gate dielectric materials affects the electrical performance and reliability of advanced HK based metal-oxide-semiconductor devices. It is important to study the role of GB in stress-induced-leakage current (SILC) degradation and time-dependent dielectric breakdown of polycrystalline HK gate stacks. In this work, we present nanoscale localized electrical study and uniform stressing analysis comparing the electrical conduction properties at grain and GB locations for blanket cerium oxide (CeO2)-based HK thin films using scanning tunneling microscopy. The results clearly reveal higher SILC degradation rate at GB sites and their vulnerability to early percolation, supporting the phenomenon of GB-assisted HK gate dielectric degradation and breakdown.
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