Polarity dependent breakdown of the high-κ/SiOx gate stack: A phenomenological explanation by scanning tunneling microscopy
ABSTRACT From scanning tunneling microscopy, we present unambiguous evidence of thermally induced localized conduction paths exhibiting an asymmetrical conduction property in the high- κ gate stack. The tunneling current under gate injection biasing is found to be much larger than that under substrate injection biasing after a 700 ° C postdeposition anneal, i.e., the localized paths exhibit a much lower resistance under gate injection biasing. This finding provides a phenomenological explanation for the polarity dependent breakdown of the high- κ gate stack as observed from electrical stressing of large-area metal-oxide-semiconductor capacitors.
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ABSTRACT: Reliability study of high-κ (HK) gate dielectric based transistors has become imperative for the current and future CMOS technology nodes as the industry shifts towards replacement of conventional silicon oxynitride (SiON) with hafnium-based oxides. One of the key requirements of any oxide reliability study is a quantitative assessment of the time dependent dielectric breakdown (TDDB) lifetime using suitable statistical models. Direct extension of the simple statistical model used for SiON to the HK is complicated by the presence of the interfacial sub-oxide layer (IL, SiO<sub>x</sub>) which is sandwiched between the HK and Si substrate. Given the dual-layer HK-IL dielectric stack, it is necessary to develop new statistical models and electrical test algorithms that can enable us to decode the reliability and Weibull slope of the individual HK and IL layers so that the relative reliability of these two layers can be studied to identify the layer which serves as a “savior” in prolonging the front end reliability of current HK based logic devices. In this study, we propose a new cumulative damage statistical model in conjunction with a two step voltage stress electrical test algorithm for sequential HK-IL breakdown which enables us to analyze the TDDB reliability of HK and IL separately.Reliability Physics Symposium (IRPS), 2010 IEEE International; 06/2010
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ABSTRACT: The presence of grain boundaries (GBs) in polycrystalline high-κ (HK) gate dielectric materials affects the electrical performance and reliability of advanced HK based metal-oxide-semiconductor devices. It is important to study the role of GB in stress-induced-leakage current (SILC) degradation and time-dependent dielectric breakdown of polycrystalline HK gate stacks. In this work, we present nanoscale localized electrical study and uniform stressing analysis comparing the electrical conduction properties at grain and GB locations for blanket cerium oxide (CeO2)-based HK thin films using scanning tunneling microscopy. The results clearly reveal higher SILC degradation rate at GB sites and their vulnerability to early percolation, supporting the phenomenon of GB-assisted HK gate dielectric degradation and breakdown.Applied Physics Letters 02/2011; 98(7):072902-072902-3. · 3.79 Impact Factor