CMOS-Integrable Piston-Type Micro-Mirror Array for Adaptive Optics Made of Mono-Crystalline Silicon using 3-D Integration
ABSTRACT This paper presents a novel CMOS-compatible fabrication process and evaluations of a micro mirror array (MMA) made of mono-crystalline silicon (m-Si) for adaptive optic (AO) applications. The m-Si mirror layer is transfer bonded from a silicon-on-insulator (SOI) donor wafer with adhesive wafer bonding towards an intermediate patterned polymer spacer layer and clamped with metal plating. We present a CMOS compatible, bond alignment-free fabrication scheme offering the potential for high air gap distances between substrate and mirrors and we show first measurements of the fabricated mirrors.
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ABSTRACT: A multimode 2×2 optical switch made from chemically micro-machined silicon piece parts is described. This switch uses microlenses, aligned to fibers by a silicon base, to expand the optical beam and relax alignment tolerances and a pivoting silicon mirrors as the switching mechanism. The moving mirror switch meets or exceeds all the requirements for FDDI applications. The switch loss is typically 0.7 dB and operates at 5 V and 30 mA. The switch insertion/deinsertion time is less than 10 ms, and the optical interruption time is less than 1 ms. The switch design, which minimizes alignments in fabrication and provides for z -axis assembly and the low cost of the high precision piece parts contribute to making this a low-cost switch to manufactureJournal of Lightwave Technology 09/1992; · 2.78 Impact Factor
Article: High fill-factor two-axis gimbaled tip-tilt-piston micromirror array actuated by self-Aligned vertical electrostatic combdrives[show abstract] [hide abstract]
ABSTRACT: In this paper, we present a high fill-factor micromirror array actuated by self-aligned vertical electrostatic combdrives. To meet the requirements of applications in free-space communication and imaging, each micromirror has three degrees of freedom of motion: rotation around two axes in the mirror plane and linear translation perpendicular to the mirror plane. Our approach is to integrate the high fill-factor reflectors into the fabrication process of the actuators on the wafer-scale. Multilevel silicon-on-insulator (SOI) bonding is utilized to form the high optical quality reflectors and high aspect-ratio vertical combdrive actuators. The wiring for electrical access to the multielectrode per pixel array is fabricated on separate wafers by thin film processing, and flip-chip bonded to the reflector/actuator chip. This architecture overcomes the fill-factor limitation of top-side accessed electrical addressing of mirrors made on SOI. Our 360μm pixel size mirror array achieves a 99% fill-factor with optically flat reflectors.Journal of Microelectromechanical Systems 07/2006; · 2.10 Impact Factor
CMOS-INTEGRABLE PISTON-TYPE MICRO-MIRROR ARRAY FOR
ADAPTIVE OPTICS MADE OF MONO-CRYSTALLINE SILICON
USING 3-D INTEGRATION
Martin Lapisa1, Fabian Zimmer2, Frank Niklaus1, Andreas Gehner2, Göran Stemme1
1Microsystem Technology Laboratory, School of Electrical Engineering
Royal Institute of Technology (KTH), Stockholm, Sweden
2Fraunhofer Institut für Photonische Mikrosysteme (IPMS), Dresden, Germany
This paper presents a novel CMOS-compatible
fabrication process and evaluations of a micro mirror
array (MMA) made of mono-crystalline silicon (m-Si) for
adaptive optic (AO) applications. The m-Si mirror layer is
transfer bonded from a silicon-on-insulator (SOI) donor
wafer with adhesive wafer bonding towards an inter-
mediate patterned polymer spacer layer and clamped with
metal plating. We present a CMOS compatible, bond
alignment-free fabrication scheme offering the potential
for high air gap distances between substrate and mirrors
and we show first measurements of the fabricated mirrors.
Micro-mirrors have found a wide range of
applications in the past decades, e.g. in projection systems
, optical scanners , optical switches  and maskless
lithography systems  to mention a few examples.
General requirements especially in high precision
applications are to achieve high mirror planarity and high
deflection reproducibility without any mechanical drift.
Usually, such deflection drifts are accompanied with
plastic deformations or imprinting originating from
material creep and internal stress relaxation processes .
However, for many applications a stable analog deflection
over a long period is vital. Therefore the use of
mechanically more stable materials has been investigated
for CMOS integration .
One of them is mono-crystalline silicon (m-Si) that
can be integrated by utilizing wafer-bonding. M-Si shows
a moderate reflectivity in the ultraviolet (UV) spectral
range but the reflectance drops in the visible and infra-red
region . Despite that m-Si shows superior mechanical
properties as it does not contain any internal stress that
might relax and it is fully elastic deformable.
Furthermore, m-Si is supplied with a very low surface
roughness without the need of additional surface
treatments. As a result, m-Si has the potential to allow for
drift-free, highly planar micro-mirror devices .
Adaptive optics (AO) for correction of phase
aberrations in the optical-path requires 2-dimensional
arrays of vertically movable micro-mirrors with µm-
stroke capabilities, high fill factor, high surface flatness,
nanometer range deflection precision and short response
times. Especially in those cases, where a high number of
actuator elements are required, the driving electronic has
to be incorporated by means of a monolithically integrated
CMOS address circuitry within the same chip. CMOS
compatibility arises constrains to allowed fabrication
methods and processes regarding the thermal budget,
radiation and applicable electric field strength.
For integration of m-Si micro-mirror arrays (MMA)
with CMOS driving circuits the assembly after processing
of MEMS and electronics on separate wafers in a flip-chip
process was reported , . In that way processing
restrictions can be bypassed for arrays with large mirrors
that offer the space for flip-chip interconnects. However,
small pixel sizes with high fill-factors cannot be realized
with this technique as the scalability of flip-chip bonding
The wafer-level integration of micro-mirrors on
CMOS driving circuits requires particle tolerant processes
that allow for high yield. Adhesive wafer bonding that
utilizes a particle insensitive adhesion layer is a well
suited integration technique , . It was successfully
used in the fabrication of tilting mirror-arrays for
maskless deep-UV lithography .
In our previously reported work  small arrays of
tilting m-Si micro-mirrors with small air gaps between
mirror and electrode was presented. The current work
focuses on the need of adaptive optic applications for
phase aberration correction. We present a process that
allows for large air gaps by utilizing a thick patterned
polymer spacer in combination with adhesive wafer
bonding of m-Si. The CMOS compatible process is wafer-
alignment free and the fabrication complexity is relatively
low. No surface finishing processes like chemical-
mechanical polishing (CMP) to achieve high mirror
flatness are required.
DESIGN & FABRICATION
The MMA consist of 96 x 96 piston-type mirrors with
40 µm pitches, a fill factor of 73% and a 2.2 µm air gap in
between mirror plate and electrode. The mirrors are
deflected in a parallel plate actuator manner.
Figure 1: Sketch of single mirror, mirror plate sectioned
To save time and costs for first evaluations of the
process technology the MMA has been implemented on
CMOS dummy devices employing fixed wired address
electrodes. The surface of these devises has not been
planarized and shows a peak-to-valley topography of 300
m-Si mirror plate
nm in between the electrodes and wires. Eight columns of
mirrors are interconnected and actuated simultaneously.
Figure 1 shows the design of a single MMA pixel.
The m-Si mirror plate is suspended on four flexures which
are connected to metal posts. The metal posts define the
air gap in between mirror plate and electrode and connect
the mirrors electrically to common ground potential.
When actuated, an electrostatic field between mirror plate
and bottom electrode creates an attractive force resulting
in a piston-like downward movement of the mirror.
Figure 2: SEM picture of a section of the fabricated
micro-mirror array with 96x96 mirrors. The
mirror layer is made from 340 nm thick mono-
Figure 2 shows a scanning-electron-microscope
(SEM) picture of a section of the fabricated mirror-array.
All mirrors are interconnected by sharing the post with the
The fabrication process of the passive MMA device is
depicted in Figure 3. The process starts with fabrication of
the bottom substrate by sputter deposition of aluminum
(AlSi2Cu0.5) onto an oxidized silicon wafer. Electrodes
and wires are etched with reactive-ion-etching (RIE) into
the metal layer. Hereafter, a thin layer of nickel is
deposited onto the aluminum in a lift-off process at the
positions of later electroless nickel plated posts (Fig.
Figure 3a). This layer is required for the auto-catalytic
chemical reaction of electroless plating to start.
The negative photoresist AZ nLOF 2070 is used as a
sacrificial layer and is spun onto the substrate in a
standard photoresist spinner. Trenches in between
electrodes and wires on the substrate cause surface
topography in the applied sacrificial polymer. To lower
the topography the resist spin-on is done in two passes. In
the first pass the photoresist is diluted to a viscosity
convenient to provide resist layer thickness of 200 nm.
The resist is spun-on for 5 s at 3000 rpm and left on the
chuck for 2 minutes to allow a reflow and the trenches to
be filled. After subsequent soft-baking non-diluted photo-
resist with a thickness of 2 µm is applied in the second
pass. A total layer thickness of 2.2 µm defines the mirror
air gap. At the positions of the plating bases openings are
photo-lithographically patterned into the resist-stack (Fig.
Figure 3b). These openings act as plating moulds later in
the process. The negative resist is thereafter fully cross-
linked by flood exposure in a mask aligner and hardened
by hard-baking in an oven for 120 minutes at 205°C.
Figure 3: 3-D integration process
For the m-Si layer transfer from the silicon-on-
insulator (SOI) donor wafer an adhesive wafer-bonding
process is used that we reported earlier . The bond-
polymer is spun-on and pre-cured on both the device layer
of the SOI-wafer and the patterned sacrificial polymer of
the substrate (Fig. Figure 3c). The wafers are bonded in a
wafer-bonder under high vacuum by applying pressure
and ramping up the temperature of the wafer stack (Fig.
Figure 3d). Bond alignment is not needed for the
assembly since the SOI-wafer does not contain any
pattern at this point. After bonding, the handle wafer is
etched away isotropically with SF6 plasma in an
inductively coupled plasma etcher (ICP). The 400 nm
thick buried oxide of the SOI wafer is an etch-stop layer
with this etch-chemistry and protects the m-Si device
layer from being attacked. Thereafter the oxide is stripped
in buffered HF (BHF), leaving only the thin device layer
of the SOI-wafer behind (Fig. Figure 3e).
The wafer alignment marks on the bottom substrate
are visible to the stepper optics through the thin m-Si
device layer and can be used for consecutive lithography
steps. Holes are etched into the m-Si layer by RIE to
access the plating moulds. The moulds are cleared from
bonding polymer in an anisotropic oxygen plasma etch to
make the underlying nickel accessible (Fig. Figure 3f).
Because the bond polymer is etched 3 times faster than
the highly cross-linked sacrificial negative resist, the latter
is almost not attacked at all in this step.
To clamp the m-Si device layer mechanically and
electrically, nickel posts are grown in the plating moulds.
Nickel deposition starts spontaneously as the nickel
platingbase gets in contact with the nickel hypophosphite
(Ni[H2PO2]2) plating solution at elevated temperatures.
The wafer is immersed into the electrolyte until nickel is
plated slightly above the edge of the m-Si device layer
(Fig. Figure 3g).
With the last lithography mask the mirror pattern is
RIE etched into the m-Si layer (Fig. Figure 3h). The wafer
is thereafter coated with a thick photoresist to protect the
surface from particles, dirt and mechanical impact that
could appear during die separation in the dicing saw.
After dicing, the mirror structures are released in
isotropic oxygen plasma in which the sacrificial resist
spacer is etched away selectively (Fig. Figure 3i).
All micro-mirror measurements are done with a
white-light interferometer from Wyko. The MMA devices
were housed in a ceramic pin grid array (PGA 68), which
can be plugged into an external driving setup.
In order to keep the number of external interconnects
limited, sub-regions of 8 mirror columns have been
electrically combined to one input and thus can be
actuated only simultaneously. Figure 4 shows a 3-D
deflection profile of a MMA section. The left part of the
array is actuated at 30 V while the right part is set to 0 V.
In this measurement the metal posts which support the
micro-mirror flexures are masked and not shown for
Figure 4: Measurement with white light interferometer.
A line-scan of this measurement is shown in Figure 5.
The scan is taken along a line in the middle of the third
row, as indicated by the green line drawn in the inset.
0 40 80 120160 200 240
Deflection Z [nm]
Position X [µm]
Figure 5: Line-scan along green marked line (inset).
Figure 6 depicts the same line scan taken from a
measurement with all mirror non-deflected.
0 4080120160 200 240
Deflection Z [nm]
Position X [µm]
Figure 6: Zero-deflection line-scan
The mirrors have a slight convex bow in the non-
deflected initial state. Apart from that a slight non-
uniformity in height is observed together with a certain tilt
of the mirrors.
0 4080 120160 200240
Deflection Z [nm]
Position X [µm]
Figure 7: Deflection profile along the green marked line
(inset), with zero-voltage surface profile
The deflection profile in Figure 7 shows the
subtracted profiles of Figure 5 and Figure 6, thus
eliminating any pre-deformation effects like initial
curvature or tilt. As can be seen, upon actuation the
mirrors undergo a warpage downwards in the center.
In this first evaluation of the process technology non-
planarized, CMOS-compatible test devices with a surface
topography of 300 nm are used to build up MMA devices.
With a 2-pass spin-on process the topography of the
sacrificial layer was lowered by 40% compared to a single
pass process and ended up at 150 nm prior bonding. In
spite of this remaining non-planarity, the micro-mirrors
show a 1σ-height deviation of only about 9 nm in the non-
deflected state. This confirms the excellent leveling
capability of the adhesive wafer-bonding process. A more
uniform height distribution can be expected on planarized
substrates such as CMOS-wafers.
In the non-deflected zero-voltage state the mirrors
show a convex curvature corresponding to a pixel RMS of
about 10 nm or a peak-to-valley value of about 25 nm.
Upon actuation, the mirrors change from their initial
convex shape to a slight concave shape. This is due to the
electrical field forces acting on the mirror plate and thus
introducing a bending towards the pixel center. The
center-deflection of the measured MMA section showed a
uniform displacement in Z-direction of 220 nm ± 5 nm at
Due to process variations, the mirrors have a
statistical spread pre-tilt of up to 50 nm. With the pre-
tilted mirrors, a pull-in deflection of about 400 nm was
reached. The RMS mirror planarity and height deviations
obtained within this first fabrication run are quite
promising to meet the requirements for most AO
applications and the maximal deflection is sufficient for
2π-phase modulation in the visible light spectrum. With
an optimized processing scheme, the observed variations
can possibly be further reduced, allowing for a reduced
pre-tilt of the mirrors.
A novel CMOS compatible fabrication technique
utilizing a patterned polymer spacer in combination with
adhesive wafer-bonding is presented. Piston-type micro-
mirror arrays consisting of 96x96 mirrors made from
mono-crystalline silicon with an air-gap of 2.2 µm were
successfully fabricated and first evaluations were
This work is part of the European project Q2M and
sponsored by the EU through its 6th Framework Program.
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