Fluorinated HfO2 gate dielectrics engineering for CMOS by pre- and post-CF4 plasma passivation
ABSTRACT In this paper, we demonstrate TaN/fluorinated HfO2 CMOS devices, focusing on symmetry and asymmetry fluorine incorporation at top or bottom HfO2 interfaces. 16% permittivity enhancement, 65% and 91% mobility increases for electron and hole, respectively, under high electric field was achieved. Reliability of n- and p-MOSFET was improved 3 orders and 8% for GIDL and hot carrier immunity, respectively. A physical model of shallow and deep trapping level affected by fluorine was proposed to explain the NBTI and PBTI improvements.
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ABSTRACT: High-k/germanium (Ge) interfaces are significantly improved through a new interface engineering scheme of using both effective pregate surface GeO<sub>2</sub> passivation and postgate dielectric (postgate) treatment incorporating fluorine (F) into a high-k/Ge gate stack. Capacitance-voltage (C-V) characteristics are significantly improved with minimum density of interface states (D<sub>it</sub>) of 2 times 10<sup>11</sup> cm<sup>-2</sup> ldr eV<sup>-1</sup> for Ge MOS capacitors. A hole mobility up to 396 cm<sup>2</sup>/V ldr s is achieved for Ge p-metal-oxide-semiconductor field-effect transistors (pMOSFETs) with equivalent oxide thickness that is ~10 Aring and gate leakage current density that is less than 10<sup>-3</sup> A/cm<sup>2</sup> at V<sub>t</sub> plusmn 1 V. A high drain current of 37.8 muA/mum at V<sub>g</sub> - V<sub>t</sub> = V<sub>d</sub> = -1.2 V is presented for a channel length of 10 mum. The Ge MOSFET interface properties are further investigated using the variable-rise-and-fall-time charge-pumping method. Over three times D<sub>it</sub> reduction in both upper and lower halves of the Ge bandgap is observed with F incorporation, which is consistent with the observation that frequency-dependent flat voltage shift is much less for samples with F incorporation in the C-V characteristics of Ge MOS capacitors.IEEE Transactions on Electron Devices 07/2009; 56(6-56):1330 - 1337. DOI:10.1109/TED.2009.2019420 · 2.47 Impact Factor
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ABSTRACT: A novel surface passivation technique using silicon nitride (SN) by - treatment has been demonstrated on -gated Ge pMOSFETs. It is found that ultrathin SN passivation is more effective to suppress the Ge out diffusion than ultrathin Si passivation. Improved interface quality and device performance were achieved for the device with the SN passivation. Fluorine (F) incorporation by postgate treatment was also implemented to further enhance the performance. Furthermore, bias temperature instability (BTI) characteristics were systematically investigated on interface engineered (Si-, SN-, or -passivated) Ge pMOSFETs by both conventional dc - and fast pulse measurement. The impact of thickness and postgate treatment processes (F incorporation) on BTI and device performance was also studied, and it is found that BTI and device performance can be improved by reducing the thickness or incorporating F.IEEE Transactions on Electron Devices 07/2010; 57(6-57):1399 - 1407. DOI:10.1109/TED.2010.2046992 · 2.47 Impact Factor
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ABSTRACT: We consider the estimation of diffeomorphic transformations aligning a known shape and its distorted observation. The classical way to solve this registration problem is to find correspondences between the shapes and then compute the transformation parameters from these landmarks. Here we propose a novel framework where the exact transformation is obtained as the solution of a polynomial system of equations. The method has been applied to 2D and 3D medical image registration, industrial inspection, planar homography estimation, etc... and its robustness has also been demonstrated. The advantage of the proposed solution is that it is fast, easy to implement, has linear time complexity, works without established correspondences and provides an exact solution regardless of the magnitude of transformation.Signal-Image Technology and Internet-Based Systems (SITIS), 2011 Seventh International Conference on; 01/2011