Conference Paper

VLSI design and analysis of low power 6T SRAM cell using cadence tool

Dept. of ECE, Maulana Azad Nat. Inst. of Technol., Bhopal
DOI: 10.1109/SMELEC.2008.4770289 Conference: Semiconductor Electronics, 2008. ICSE 2008. IEEE International Conference on
Source: IEEE Xplore

ABSTRACT CMOS SRAM cell is very less power consuming and have less read and write time. Higher cell ratios can decrease the read and write time and improve stability. PMOS transistor with less width reduces the power consumption. This paper implements 6T SRAM cell with reduced read and write time, area and power consumption. It has been noticed often that increased memory capacity increases the bit-line parasitic capacitance which in turn slows down voltage sensing and make bit-line voltage swings energy expensive. This result in slower and more energy hungry memories.. In this paper Two SRAM cell is being designed for 4 Kb of memory core with supply voltage 1.8 V. A technique of global bit line is used for reducing the power consumption and increasing the memory capacity.

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    ABSTRACT: In this paper a new 5T SRAM cell is proposed with fast performance, high density and low power consumption. The proposed CMOS SRAM cell consumes less power and has less read and write time. It is capable of storing the bits effectively. The novel cell size is 24.37% smaller than the conventional six-transistor SRAM cell using same design rules without any performance degradation. Simulation results show that there is substantial improvement in performance of the proposed cell as regards performance parameters like delay, power consumption and leakage current. The novel configuration has been analyzed using cadence virtuoso tool in 45nm technology node.
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