Experimental Study and Statistical Analysis of Solution-Shearing Processed Organic Transistors Based on an Asymmetric Small-Molecule Semiconductor
ABSTRACT Solution processed organic field-effect transistors (SPOFETs) are crucial for realizing low-cost large-area/ubiquitous flexible electronics. Currently, both soluble high-mobility organic semiconductors and efficient solution processes are in demand. In this paper, we report the systematic experimental study and statistical modeling/analysis for the SPOFETs based on an asymmetric small-molecule organic semiconductor, trimethyl-[2, 2'; 5', 2''; 5'', 2'''] quarter-thiophen-5-yl-silane (4 T-TMS), which was deposited as the active layer through a recently developed low-temperature solution-shearing process. Three-dimensional statistical modeling and analysis bas ed on 46 different processing conditions was used to comprehensively study the solution-shearing process control and optimization for fabricating high-performance 4T-TMS SPOFETs. Various effects including solution concentration effect, shearing speed effect, and deposition temperature effect were investigated and discussed. Under optimized processing conditions, well-oriented crystalline 4 T-TMS thin films were deposited for the SPOFETs, which showed remarkable effective field-effect mobility up to 0.3 cm2/V middots in the saturation region and current on/off ratios over 106. Gaussian fitted uniformity and good air stability of these devices stored and tested under ambient conditions for six months suggest that 4 T-TMS SPOFETs based on the optimized solution-shearing process are promising for applications in organic electronic circuits and displays. Importantly, the systematic experiment design and the corresponding statistical modeling/analysis presented here provide a general guideline for process optimization for fabricating high-performance SPOFETs.
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ABSTRACT: We demonstrate low-voltage, solution-processed organic transistors on rough plastic substrates with a carrier mobility over 0.2 cm2/V s, a turn-on voltage of near 0 V, and a record low subthreshold slope of ∼ 80 mV/decade in ambient conditions. These exceptional characteristics are attributed to (1) a device stacking architecture with a conducting polymeric gate and a double layered dielectric composed of low-temperature cross-linked poly(4-vinylphenol), (2) a low interface trap density achieved by modifying the dielectric surface with a phenyl-terminated self-assembled monolayer from 4-phenylbutyltrichlorosilane, and (3) controlled crystallization of a small-molecule organic semiconductor film with favorable charge transport microstructure and a low bulk trap density as deposited by an optimized solution-shearing process. The device performance under different operating voltages was also examined and discussed.Applied Physics Letters 05/2009; 94(20):203301-203301-3. DOI:10.1063/1.3133902 · 3.52 Impact Factor
- Journal of Materials Science 01/2010; 45(2):566-569. DOI:10.1007/s10853-009-4047-x · 2.37 Impact Factor