A low power dynamic pseudo random bit generator for test pattern generation
ABSTRACT Pseudo random bit generator is widely used in BIST for test pattern generation. Typical pseudo random bit generator adopts linear feedback shift register (LFSR) as its basic circuit. Dynamic LFSR (DLFSR) which has better cryptographic properties with respect to typical LFSR consumes more power. This paper forwards a low power DLFSR (LDLFSR) circuit which achieves comparable performance with less power consumption. Typical LFSR, a DFLSR, a LDLFSR are compared on randomness property and inviolability property. Multi-layer perceptron neural networks are used to test these LFSRsÂ¿ inviolability property. Result shows that LDLFSR keeps comparable performance with a 7% power reduction and a 5.6% area reduction.
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ABSTRACT: Test power is the major issue for current generation VLSI testing. It has become the biggest concern for today's SoC. While reducing the design efforts, the modular design approach in SoC (i.e., use of IP cores in SoC) has further exaggerated the test power issue. It is not easy to select an effective low-power testing strategy from a large pool of diverse available techniques. To find the proper solutions for test power reduction strategy for IP core-based SoC, in this paper, starting from the terminology and models for power consumption during test, the state of the art in low-power testing is presented. The paper contains the detailed survey on various power reduction techniques proposed for all aspects of testing like external testing, Built-In Self-Test techniques, and the advances in DFT techniques emphasizing low power. Further, all the available low-power testing techniques are strongly analyzed for their suitability to IP core-based SoC.VLSI Design 01/2011;
- VLSI Design. 01/2011; 2011.