A Built-In Self-Test (BIST) Technique for Single-Event Testing in Digital Circuits

Abstract

A built-in self-test technique for testing digital logic circuits for single-events has been developed. The BIST technique can be used for single-event testing in any conventional laboratory to evaluate the circuit level response to SEs. Experimental and simulation results for multiple technology nodes show the feasibility of this approach to test circuits, with the added advantages of reduced testing time and cost.

Full text

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A BUILT-IN SELF-TEST (BIST) TECHNIQUE FOR SINGLE-EVENT
TRANSIENT TESTING IN DIGITAL CIRCUITS



By

Anitha Balasubramanian


Thesis
Submitted to the Faculty of the
Graduate School of Vanderbilt University
in partial fulfillment of the requirements
for the degree of

MASTER OF SCIENCE
in
Electrical Engineering

August, 2008
Nashville, Tennessee
Approved by:
Professor Bharat L. Bhuva
Professor Lloyd W. Massengill

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ACKNOWLEDGMENTS

First and foremost, I would like to express my gratefulness to God for all his
blessings. I am indebted to my advisor, Dr. Bharat L. Bhuva who has always been there
to support, advice and direct me in my work. I can count the number of days that I have
not been in his office without a question to ask. He has been very patient with me and
has always given me ideas when results were hard to come by.
I would like to thank Dr.Massengill for his invaluable comments he offered for
my research work. I would also like to thank Balaji Narasimham for his spontaneous
help, especially at the beginning of my project. My special thanks also goes to Robert
Shuler from NASA, JSC for helping me with my research work by fabricating my
design. I would like to specially thank Daniel, Megan, Matt and Wole and also all the
other members of the RER group for the help offered during the course of this work. I
am also very thankful to all my professors for the time and effort they put into our
weekly RER meetings to give valuable suggestions to students.
My husband Mr.Vijay Chandramouli, has been my constant source of
motivation, pushing me to strive harder and achieve more. He was always there for me,
especially during difficult times of research, and gave me the courage and assurance to
move on. I am deeply indebted to my sister Anupama and her husband Karthik, who
have been responsible for me coming to Vanderbilt. They have been of great moral
support and have at all times given me a shoulder to lean on throughout my stay at
Vanderbilt. Anu has always been the first person I have approached for any technical
help or suggestion and she has guided me in every way possible.

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Finally, all this would not have been possible without the love, support and
encouragement of my parents Dr. & Mrs. Balasubramanian and my in-laws Mrs. & Mr.
R. Chandramouli. I would also like to express thanks to my grandmother Mrs. Parvathy,
my aunt and uncle Mrs. & Mr. Jayashankar, my cousins Nikhil and Nina and also my
brother-in-law and sister-in-law Mahesh and Sowmya, who have always been a very
supportive family.

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TABLE OF CONTENTS

Page
ACKNOWLEDGEMENTS............................................................................................. ii
LIST OF FIGURES..........................................................................................................vi
Chapter
I. INTRODUCTION..........................................................................................................1
SETs and their Significance with CMOS Scaling.................................................1
Testing of Circuits for SETs ............................….................................................4
Overview of thesis.................................................................................................6

II. SINGLE-EVENT TRANSIENT PULSE CHARACTERISTICS................................8
SET Formation.......................................................................................................8
Circuit Model for SET Charge Collection.............................................................9
SET Modeling in Hardware……….....................................................................10

III. BUILT-IN SELF-TEST (BIST) TECHNIQUE........................................................13
SET Control Parameters......................................................................................13
Technique to Control Pulse Width......................................................................18
Technique to Control Pulse Arrival.....................................................................18
Single-Event Transient Pulse-Generate Circuit...................................................19
Implementation in a Self-Test Mechanism..........................................................20

IV. SIMULATION/EXPERIMENTAL RESULTS........................................................24
Simulation Results………...................................................................................24
Experimental Results...........................................................................................26
On-chip Measurements............................................................................27
Off-chip Measurements...........................................................................29

V. IMPLEMENTATION OF BIST IN DIGITAL CIRCUITS.......................................32
Transients in CMOS Digital Logic Circuits........................................................32

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Identification of Insertion Nodes.........................................................................34
BIST in a 16-bit Adder........................................................................................35
BIST in a 4-bit Multiplier....................................................................................38
Pulse Injection.....................................................................................................40

CONCLUSIONS….........................................................................................................43
APPENDIX….................................................................................................................45
REFERENCES................................................................................................................51

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LIST OF FIGURES

Figure

Page
1. Typical shape of the SE charge collection current at a junction...................................9
2. Typical shape of the SE current pulse for advanced technologies................................9
3. Inverter string showing an n-hit at node ‘x’................................................................10
4. Voltage transients at hit node ‘x’ and one node after hit node ‘y’..............................11
5. D-type flip-flop containing 6 NAND gates and an input inverter...............................15
6. Primary SET pulse parameters....................................................................................17
7. Technique to create pulses of multiple widths based on delay set by the delay
chain................................................................................................................................18
8. Technique to control transient onset w.r.t to a synchronous input..............................19
9. Circuit to generate SETs of varying arrival times and pulse widths...........................19
10. A Linear Feedback Shift Register (LFSR) ...............................................................20
11. LFSR with a decoder that sets the inverter delay......................................................22
12. Sample simulations showing variation in pulse width and arrival............................24
13. Pulse width as a function of the current-starved inverter’s control voltage..............25
14. Pulse-Generate circuit with a series of 4 current-starved inverter chain as delay
elements...........................................................................................................................26
15. Layout of fabricated IC; red oval indicates location of Pulse-Generate circuit........27
16. Measurements taken on-chip with Pulse-Capture circuit..........................................28
17. Pulse arriving close to the rising edge of the clock……….......................................30
18. Pulse arriving close to the falling edge of the clock..................................................30
19. Block diagram of a half-adder...................................................................................36

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20. Distribution of soft errors for all nodes and insertion nodes (80% coverage) using
BIST in a 16-bit adder.....................................................................................................36
21. A 4bit-multiplier........................................................................................................38
22. Distribution of soft errors for all nodes and insertion nodes (88% coverage) using
BIST in a 4-bit multiplier................................................................................................39
23. Multiplexer design to inject a transient pulse into a logic node................................41

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CHAPTER I



INTRODUCTION


The radiation effects community has been studying and analyzing the effects of
radiation on space-based and terrestrial-based electronics for the past four to five
decades. The radiation environment is populated with electrons, protons, cosmic rays
and ions, which have sufficient energy to ionize the material through which they pass. A
single-event effect (SEE) results from a single energetic particle that strikes a micro-
electronic device causing device malfunction. Single-event phenomena can be classified
into hard or soft errors depending on whether the ions cause permanent damage or
temporary malfunctioning of the circuit they strike. Some common SEEs are i) single-
event upset (SEU) ii) single-event transient (SET) iii) single-event latchup (SEL) and
iv) single-event burnout (SEB). This thesis primarily deals with two types of single-
event phenomena- SETs and SEUs that occur in digital logic micro-electronic circuits,
and a novel built-in testing technique to assess their vulnerability to these SEs.

SETs and their Significance with CMOS Scaling
Single-event transients were first identified following an in-flight anomaly in the
TOPEX POSEIDON spacecraft [1]. SETs are caused by ionizing radiation passing
directly through or near the p-n junction of a semiconductor device, and are defined as
momentary voltage excursions at a node of an integrated circuit. Depending on the
operating conditions of the micro-electronic device, the voltage spike may propagate
away from the node it was generated at, and eventually appear at the output of the

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circuit. At the circuit output it may appear as the same voltage transient, an amplified
or attenuated version of the original transient, or as a change in the expected logical
output. If the voltage spike is captured by a sequential element such as a latch in the
micro-electronic circuit, an SET becomes a single–event upset (SEU), resulting in a
static error leading to disruption in circuit operation. An SEU is a type of SEE and is
defined as a static upset in storage cells such as latches and flip-flops.
Until recently, the radiation community has not been very concerned about SETs
being a reason for flawed operation of micro-electronic circuits. In older technologies
with minimum feature sizes being larger than 0.3 µm, SETs did not have a high
probability of being captured [2]. As minimum dimensions of the integrated circuits
(ICs) continue to decrease to yield high density and high performance circuits, their
susceptibility to SETs has also increased significantly [3]-[15]. With technology
scaling, SETs are becoming a larger source of soft errors in digital circuits for primarily
two reasons. Firstly, it is the scaling of nodes. In the past, nodal capacitances were
larger and only ions with a high Linear Energy Transfer (LET) striking the device could
cause an SET. But with minimum feature sizes having reached the sub-micron level,
nodal scaling has reduced nodal capacitances, allowing more SETs having sufficient
pulse width and amplitude to be formed. The amount of charge differentiating logic
HIGH from logic LOW has decreased [4], increasing the probability for SETs to occur.
Secondly the increasing frequency of circuit operation leads to a higher probability of
SET pulse capture [10],[11],[16].
In the sub-micron technologies, the major source of soft errors results from
combinational logic cells as against from sequential cells. Recent research has shown

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that the potential for soft errors increases dramatically because the error cross-section of
combinational logic may far exceed that of traditional latch structures. There has been
as much as a 5-10 times increase in the number of combinational gates in a particular
design compared with static-latch cells [16]. The following references discuss in detail
the effects of SETs on devices and their propagation through combinational logic [3],
[17]-[22]. All these factors contribute to the capture of a substantial fraction of these
transients generated in combinational logic; due to the higher operating frequencies and
lower charge requirements in advanced deep sub-micron technologies [4],[16].
Additionally, upset error rates caused by SETs are a strong function of the SET
pulse width, arrival time of an SET with respect to the clock edge and clock frequency
[11][16]. When an SET occurs in a combinational logic node (such as an inverter or a
NAND gate), it may propagate and potentially become latched in a static cell. In order
to become latched and cause an error, the SET pulse must have sufficient width and
amplitude and must coincide with a valid clock window for latching. This is because,
for an SET to be captured by a latch, it is required that an SET arrives within the set-up
and hold time requirements of the latch [3]. Slower clock frequencies in older
technologies provided relatively fewer clock edges for this latching to occur.
Conversely, due to GHz range scale of operation in advanced technologies, CMOS
digital logic circuits exhibit higher sensitivity to SETs. Also, as device capacitances
have scaled with the sub-micron technologies, these SETs are able to propagate more
easily through several gates without attenuation and have a higher likelihood to be
captured by latches and other sequential elements.

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Testing of circuits for SETs
The errors due to SETs are expected to dominate the overall error rate of the
entire circuit [3], [10], [16]-[12], [23], as described in the previous section. For future
technologies, the feature sizes of digital circuits will continue to shrink making them
even more susceptible to these SEEs. Research has shown that SETs are a concern not
only to space based electronics, but also to ground based systems with small feature
sizes [24]. Hence, it is of paramount importance to design and manufacture circuits that
have a high degree of immunity to SEEs. Amongst several other things, this will require
extensive testing on part of the researchers to improve understanding of the physics
involved behind the ionic interactions, to develop and check new designs for SEE and
SET sensitivity. This can help assure that circuits meet a specific minimum level of
SEE tolerance in order to be deployed in space or for use in terrestrial electronics.
Ideally, SET testing has to be done in the actual environment where the
electronic circuits will operate. Since this is not practical for circuits intended for space
applications due to extremely high costs associated and the long time requirements
involved, other alternative methods of testing have to be resorted to. Widely used
testing alternatives are with accelerators (heavy ion, neutron, proton) and pulsed laser
techniques [25]. As much as these testing procedures mimic the space environment,
there is the inconvenience of testing at a facility remote from the manufacturing or
assembly plant. Also, most accelerators are not configured to provide information on
the spatial and temporal dependence of SEE [20]. Accelerator testing can also cause
displacement damage to the semiconductor material. Testing an IC in a heavy ion beam
for short time duration with a predetermined set of random test vectors may not identify

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the most vulnerable conditions or actual error rate that will be observed in the radiation
environment.
Laser testing is more convenient as the laser light can be used to deposit energy
at small spots for identifying areas sensitive to SEUs. The arrival time of a laser light
pulse can also be synchronized to the circuit clock for measuring the time interval
during which a node is receptive to an SEU. But due to device scaling, vulnerable areas
become smaller than the size of the laser beam making it difficult to measure thresholds
accurately as the amount of energy needed to produce an SET is very sensitive to the
position of the beam. Additionally, metal fill makes it harder to test devices from the
front side with laser. Backside testing with a laser is very complicated as well. It has to
be kept in mind that both the accelerator and laser facilities are incidentally very
expensive considering the manpower, mask sets that need to be used, beam time,
fabrication costs and equipment. As the SET pulse width is a function of not only the
base technology, but also circuit parameters such as nodal capacitance, device currents,
and supply voltage [16], it is essential that SET characterization be performed for every
IC design. But, the difficulty with such a testing approach is the overhead in terms of
cost, time and testing challenges. In the past, researchers have also emulated radiation
environments by injecting errors in circuits by using codes in software, but such
techniques may not accurately include several circuit level parasitic effects [26]-[34].
This thesis describes new design methods that can be adopted for SET testing of digital
logic circuits.

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Overview of Thesis
As the cost and time involved with these conventional testing methods are very
expensive, lab-based built-in self-testing approaches that can estimate error rates due to
SETs in digital circuits can be an attractive alternative [35]-[41]. In this thesis, a new
built-in self-test design is presented, that allows for SET testing of any complex circuit
using laboratory-based equipment without the need for expensive heavy ion or laser
testing. The proposed technique electrically injects pulses similar to SETs at the chosen
nodes of a circuit for estimating the overall susceptibility of the same. The methodology
illustrated in this thesis can be used for a variety of measurements, including
(i)
providing circuit designers with information for improving SET
immunity of tested circuits
(ii)
determining the reason behind failure of circuits to meet designed levels
of SET tolerance
(iii)
measuring relative levels of SET susceptibility for hardness assurance
(iv)
understanding and studying the fundamental mechanisms responsible for
SETs
The following chapters of the thesis describes how an SET pulse is modeled in
hardware, the technique behind the generation and injection of SET pulses, and the
simulation and experimental results that compliment this design procedure.
Furthermore, this technique is applied to a couple of commonly used digital logic
circuits, illustrating the steps involved in the application of this testing scheme. The
injected SET pulses have randomly varying characteristics to mimic actual SET pulses,
to evaluate the radiation response of the circuit with the added advantage of reduced

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cost and time requirements. The advantages of the Built-in Self-Test (BIST) method of
testing over other testing methods are
(i)
requires no specialized external equipment or manpower and can be
performed in any conventional laboratory
(ii)
electrical injection of pulses do not cause any damage to the
semiconductor material/circuits evaluated
(iii)
may be used to inject pulses simultaneously at multiple nodes to test
for multi-bit upsets
(iv)
electrical injection of pulses can be controlled precisely, or can be
made completely random as well, depending on the circuit and
application for which the testing is done
(v)
it incurs minimal cost and testing time requirements

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CHAPTER II



SINGLE-EVENT TRANSIENT PULSE CHARACTERISTICS



As the built-in self-test procedure requires that pulses be electrically injected
into the circuit under test, the pulses have to be generated in hardware. In order to
generate pulses similar to SETs through circuit design, it is essential to understand how
an SET is formed, and what characteristics of an SET are important in understanding
and analyzing the circuit response to SETs. The following sections discusses the
outcomes that result from a single-event strike, how an SET is formed and what
parameters of the SET to realize in hardware.


SET Formation

When a single-event hit occurs at a node, it results in charge generation,
followed by charge collection and circuit response [42]. These three primary factors
result in the formation of an SET. The ionic interaction with semiconductor materials
results in charge deposition or generation depending on whether the ion strikes the drain
of an nmos or pmos transistor. The amount of charge generated/deposited at the struck
node depends on the properties of the particle such as the ion species, energy and angle
at which it strikes the semiconductor device. It also depends on the properties of the
semiconductor material such as its doping and junction depth. The charge
generation/deposition is generally modeled in simulations by a current source at the
struck node [42]. Device parameters such as the current drive, size of the transistors and