A Methodology to Characterize Device-level Endurance in 1T1C (1-Transistor and 1-Capacitor) FRAM
Technology-Development Team 2, Semiconductor R&D center, Memory Division, Samsung Electronics Co. Ltd., San #24, Nongseo-Dong, Giheung-Gu, Yongin-City, Kyungki-Do, KoreaDOI: 10.1109/ISAF.2008.4693962 Conference: Applications of Ferroelectrics, 2008. ISAF 2008. 17th IEEE International Symposium on the, Volume: 1
Source: IEEE Xplore
We present a mimicking methodology to describe device-level endurance in a 1T1C, 64 Mb FRAM (ferroelectric random access memory). Device-level endurance of FRAM must clarify all the issues raised from destructive read-out READ/WRITE. To explore endurance properties in a real-time operational situation, we have established a measurement set-up that covers asymmetric pulse chains corresponding to Data 1 (D1) and Data 0 (D0) READ/RESTORE over a frequency range from 1.0 to 7.7 MHz. The cycle-to-failure of 5.9 ?? 1024 cycles in an operational condition of 7.7 MHz and 85 ??C, has been obtained from extrapolation to VDD = 2.0 V in a voltage acceleration. We compare testing results with those of D1??D0 populations of bit-line potential.
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