An 11-bit 8.6GHz direct digital synthesizer MMIC with 10-bit segmented nonlinear DAC

Abstract

This paper presents a low power, high speed and high resolution SiGe DDS MMIC with 11-bit phase and 10-bit amplitude resolutions. Using more than twenty thousand transistors, including an 11-bit pipeline accumulator, a 6-bit coarse DAC and seven 3-bit fine DACs, the core area of the DDS is 3 times 2.5 mm². The maximum clock frequency was measured at 8.6 GHz with 4.2958 GHz output. The DDS consumes a power of 4.8 W under a 3.3 V power supply. It achieves the best reported phase and amplitude resolutions and the best power efficiency figure of merit (FOM) 182 GHz ldr 2^ENOB/W. The measured SFDR is approximately 40 dBc with 4.2958 GHz Nyquist output and 48 dBc with 4.2 MHz output at the maximum clock frequency of 8.6 GHz. The chip was measured using LCC-52 packages.

Full text

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An 11-bit 8.6GHz Direct Digital Synthesizer MMIC
with 10-bit Segmented Nonlinear DAC
Xueyang Geng, Xuefeng Yu, Fa Foster Dai, J. David Irwin and Richard C. Jaeger
Department of Electrical and Computer Engineering, Auburn University
Auburn, AL 36849-5201, USA
Email: {gengxue,yuxuefe,fosterdai,irwinjd,jaegerc}@auburn.edu
Abstract—This paper presents a low power, high speed and
high resolution SiGe DDS MMIC with 11-bit phase and 10-
bit amplitude resolutions. Using more than twenty thousand
transistors, including an 11-bit pipeline accumulator, a 6-bit
coarse DAC and seven 3-bit fine DACs, the core area of the DDS
is 3 × 2.5mm2. The maximum clock frequency was measured
at 8.6GHz with 4.2958GHz output. The DDS consumes a power
of 4.8W under a 3.3V power supply. It achieves the best reported
phase and amplitude resolutions and the best power efficiency
figure of merit (FOM) 182GHz · 2ENOB/W. The measured
SFDR is approximately 40dBc with 4.2958GHz Nyquist output
and 48dBc with 4.2MHz output at the maximum clock frequency
of 8.6GHz. The chip was measured using LCC-52 packages.
I. INTRODUCTION
Ultra high-speed heterojunction transistors (HBT) allow
a direct digital synthesizer (DDS) to operate at mm-wave
frequency, a preferable solution to synthesis of sine waveforms
with fine frequency resolution, fast channel switching and ver-
satile modulation capability. There are several high speed DDS
designs reported with clock frequencies from 9GHz to 32GHz
and DAC resolution from 5 bits to maximum of 8 bits [1]–[3].
The maximum achieved spurious-free dynamic range (SFDR)
in previous DDS designs is approximately 30dBc, which is not
sufficient for typical radar and wireless applications. These
ultra-high speed DDSs have been implemented in indium
phosphide (InP) (HBT) technology and only tested on wafer
[1]–[3]. The DDS described in this paper employs a 0.13μm
silicon germanium (SiGe) BiCMOS technology, which is less
expensive, more robust and has higher yield than the InP
devices. The design presented here achieves 11-bit phase and
10-bit amplitude resolutions with maximum clock frequency
of 8.6GHz. It consumes 4.8W with the best reported power
efficiency figure of merit (FOM) of 182GHz·2ENOB/W and
the best reported SFDR of 40dBc.
II. ROM-LESS DDS WITH SEGMENTED NONLINEAR
DACS
The proposed DDS adopts a ROM-less architecture which
combines both the sine/cosine mapping and digital-to-analog
conversion together in a sine-weighted nonlinear digital-to-
analog converter (DAC). The block diagram of the 11-bit
8.6GHz ROM-less DDS with nonlinear DAC is shown in Fig.
1. The major part of the ROM-less DDS is an 11-bit pipeline
phase accumulator and a 10-bit segmented current-steering
nonlinear DAC, which includes a 6-bit coarse DAC and seven
Fig. 1.Diagram of the 11-bit ROM-less DDS with 10-bit segmented DAC.
3-bit fine DACs. The 10-bit frequency control word (FCW)
feeds the accumulator which controls the output frequency of
the synthesized sine waveform. Since the output frequency
cannot exceed the Nyquist rate, the MSB of the accumulator
input is tied to zero. The two most significant bits (MSB) of
the accumulator output are used to determine the quadrant of
the sine waveform. The MSB output of the phase accumulator
is used to provide the proper mirroring of the sine waveform
about the π phase point. The 2nd MSB is used to invert
the remaining 9 bits for the 2nd and 4th quadrants of the
sine waveform by a complementor, and the outputs of the
complementor are applied to the segmented nonlinear DAC to
form a quarter of the sine waveform.
Under a 3.3V power supply and a SiGe HBT base-collector
voltage of 0.85V∼0.9V, all the digital logic is implemented
using 3 level current mode logic (CML) with differential
output swings of 400mV. For an 11-bit DDS using CML
logic, power consumption is the biggest issue. Each tail current
in a CML gate is set to 0.3mA, close to 40% of peak fT
current instead of traditionally 70∼80%. Otherwise the power
consumption will exceed 9.0W. A tradeoff has been made
between operating speed and consumed power.
A. 11-bit Pipeline Accumulator
To achieve the maximum operating speed with a fixed FCW,
a pipeline accumulator is used in this design. It uses the most
hardware, but achieves the fastest speed. The total delay of
the accumulator is one full adder (FA) propagation delay plus
one D-flip-flop (DFF) propagation delay. Fig. 2 illustrates the
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Fig. 2. 11-bit pipeline phase accumulator.
architecture of the 11-bit pipeline phase accumulator, which
has a total of 11 pipelined rows. Each row has a total of 12
DFF delay stages placed at the input and output of a 1-bit
FA. Eleven DFFs are needed for a pipeline accumulator. One
more DFF for each row is used to retime the signal for layout
consideration. It will retime the signal after the metal wire
delay from the accumulator output to its input. Obviously,
the pipeline accumulator has a propagation delay of 11 clock
cycles, including a latency period equals to 10 clock cycles
plus one retiming clock cycle. Note that an accumulator needs
at least one delay stage even without any pipelined stages. The
pipeline accumulator shown in Fig. 2 allows that the 11-bit
accumulator to operate at the speed of a 1-bit accumulator
consisting of an FA and a DFF.
B. 10-bit Segmented Nonlinear DAC
The structure of the nonlinear DAC is shown in Fig. 3. To
reduce the complexity of the nonlinear DAC, segmentation has
been employed. Since the quadrant of the sine waveform was
determined by the two MSBs, a 9-bit segmented sine-weighted
DAC is used to generate the amplitude for a quarter phase (0∼
π/2) sine wave. The 9-bit sine-weighted DAC is divided into
a 6-bit thermometer decoded coarse nonlinear DAC and seven
3-bit thermometer decoded fine nonlinear DACs. The first 6
bits of the complementor outputs control the coarse nonlinear
DAC, and the highest 3 bits also address the selection of the
fine DACs. The lowest 3 bits of the complementor outputs
determinate the output value of each fine DACs.
There are several approaches on the DAC segmentation
methods [1], [4]. If we quantize the phase word of a quarter
sine wave to a + b + c bits, we have:
?π
+ cos
2a+b+c
sin
2·α + β + γ
2a+b+c
?π
?
= sin
?π
?
2·α + β
2a+b+c
?π
?
γ
2·α + βavg
· sin
2·
2a+b+c
?
(1)
where 0 ≤ α ≤ 2a−1,0 ≤ β ≤ 2b,and 0 ≤ γ ≤ 2c.
For a 3-level CML logic, setting a = b = c = 3 results
in a segmentation with the best power efficiency, since 3-to-7
Fig. 3.Diagram of 10-bit segmented nonlinear DAC.
thermometer decoder circuit can be implement using one stage
CML gate. With 11-bit phase and 10-bit amplitude resolutions,
the equations below are used to generate the coarse and fine
DAC current matrices shown in Fig. 4.
⎧
⎪
⎧
⎪
⎪
Ik=
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎩
⎪
⎪
⎨
??210− 1?sin
??210− 1?sin
?
?2π(α+β+0.5)
?1 ≤ α ≤ 7, 1 ≤ β ≤ 7 · 27?
??210− 1?cos
??210− 1?cos
−
2π(0.5)
211
?
?,(α = β = 0)
?
211
−
k−1
?
n=0
In?,
(2)
Iα,m=
⎪
⎪
⎪
⎪
⎪
⎪
⎨
⎩
?2π(α+βavg)
?2π(α+βavg)
211
?
?
sin
?
?
2π(0.5)
211
(m = 0)
2π(m+0.5)
211
?
?,
211
m−1
?
sin
?
n=0
Iα,n?,(1 ≤ m ≤ 7)
(3)
The coarse DAC current source matrix provides 512 unit
current sources. Each fine DAC has about 8 unit current
sources used to interpolate the coarse DAC. The unit current of
each current source is set at 26μA. The largest current in the
current source is 338μA, which is composed of 13 unit current
sources. The current switch contains two differential pairs with
cascode current sources for better isolation and current mirror
accuracy. The current outputs are converted to differential
voltages by a pair of off-chip 15 Ω pull-up resistors. Fig.
4 shows that the currents from the cascode current sources
are fed to outputs OUTp and OUTm by pairs of switches
(Mswitch). The MSB controls the selection between different
half periods. The current switch contains two differential pairs
with minimum size transistors and a cascode transistor to
isolate the current sources from the switches, which improves
the bandwidth of the switching circuits.
For the layout, considering the current source matching,
each current source is split into four identical small current
sources which carry a quarter of the required current. A
quadrature layout style is adopted to improve the matching
and linearity. To further improve their matching, all the current
source transistors, including coarse DAC and fine DACs,
are randomly distributed in the current source matrix and a
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Fig. 4. Current switch circuit of the nonlinear DAC.
random-walk scheme [5] was used for the current switches.
Two dummy rows and columns have been added around the
current source array to avoid edge effects. In order to minimize
the phase difference of the clock to the DFFs, an H-tree clock
scheme is used to make the clock signal reach each block
simultaneously.
III. EXPERIMENT RESULTS
The die photo of the SiGe DDS MMIC is shown in
Fig. 5. This DDS design is quite compact with an active
area of 3 × 2.5mm2and a total die area of 4 × 3.5mm2.
The DDS is tested in a 52 pin ceramic leadless package.
Figs. 6-10 illustrate the measured DDS output spectra and
waveforms for different outputs and clock frequencies. Fig.
6 presents a 4.2MHz DDS output spectrum with an 8.6GHz
clock input, with the minimum FCW of 1. The measured
output power is approximately -8.3dBm and the measured
SFDR is about 48dBc. The tone at 91.7MHz comes from the
nearby campus FM radio station. Fig. 7 shows the waveform
for the spectrum of Fig. 6. Fig. 8 and Fig. 9 demonstrate
the operation of the DDS at maximum clock of 8.6GHz with
Nyquist output (i.e., FCW=1023). Thus, the output frequency
is set as
211
× fclk = 4.2958GHz. The first order image
tone due to mixing of the clock frequency and the DDS output
frequency occurs at 8.6GHz − 4.2958GHz = 4.3042GHz,
as shown in Fig. 9. The measured SFDR of the device is
approximately 40dBc. The tone at 91.7MHz appears again
in the spectrum. Fig. 10 gives the measured DDS output
waveform with 4.2958GHz Nyquist output and 8.6GHz clock.
The enveloped signal frequency results from mixing output
and its image, which is210+1
All measurements were done with packaged parts and without
calibrating the losses of the cables and PCB tracks.
To evaluate the performance of mm-wave DDSs, a power
efficiency figure of merit can be defined as
210−1
211 ×fclk−210−1
211 ×fclk≈ 8.4MHz.
FOM =MaxClock (GHz) × 2ENOB
Power(W)
.
(4)
Fig. 5.Die photo of the 11-bit ROM-less DDS.
Fig. 6.
maximum 8.6GHz clock (FCW=1), showing about 48dBc SFDR. The tone at
91.7MHz is from the nearby campus FM radio station.
Measured DDS output spectrum with 4.2MHz output and the
Table I compares mm-wave DDS MMIC performances. Com-
pared to the InP DDS MMICs, this SiGe DDS greatly im-
proves the resolution and is the most complicated design
with approximately twenty thousand transistors. Most of the
InP DDS MMICs were measured using probe stations [2],
[3], while this DDS RFIC was packaged. The package has
a thermal resistance of approximately 30◦C. With 4.8W
power consumption at room ambient temperature, the junc-
tion temperature of the SiGe devices can reach as high as
180◦C theoretically. At such high temperature, the device
performance is greatly degraded and the DAC current switches
are no longer synchronized due to increased internal delays,
which introduce noticeable distortion to the output waveform.
When the device is cooled, the DDS can operate at the max-
imum clock frequency of 8.6GHz. At room temperature, the
packaged DDS can operate at the maximum clock frequency
of 7.2GHz. When compared with the 9-bit 9.6GHz DDS [6],
this design achieves two more phase and amplitude bits. As
a result, this DDS achieves 10 dB larger SFDR and one third
more power efficiency FOM.
IV. CONCLUSION
Implemented in a 0.13μm SiGe BiCMOS technology with
fT/fmax of 200/250GHz, this paper presented an 11-bit
8.6GHz SiGe DDS MMIC design with a 10-bit segmented
sine-weighted DAC. With Nyquist output, the DDS achieves a
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TABLE I
MM-WAVE DDS MMIC PERFORMANCE COMPARISION
Technology fT/fmax [GHz]
Phase resolution [bit]
Amplitude resolution [bit]
Max clock [GHz]
SFDR [dBc]
Power consumption [W]
Die area [mm2]
FOM [GHz · 2ENOB/W]
InP 137/267 [1]
8
7
9.2
30
15
8x5
16.0
InP 300/300 [2]
8
7
13
26.67
5.42
2.7x1.45
42.6
InP 300/300 [3]
8
5
32
21.56
9.45
2.7x1.45
34.8
SiGe 100/120 [6]
9
8
9.6
30
1.9
3x3
131.9
SiGe 200/250 [this work]
11
10
8.6
40
4.8
4x3.5
182.0
Fig. 7.
clock.
Measured DDS output waveform with 4.2MHz output and 8.6GHz
Fig. 8. Measured DDS Nyquist output spectrum with 4.2958GHz output and
the maximum 8.6GHz clock (FCW=1023), showing about 40dBc SFDR. The
tone at 91.7MHz is from the nearby campus FM radio station. The image
tone locates at 4.3042GHz.
Fig. 9.
with 8.6GHz clock. The output frequency is 4.2958GHz and the alias image
is 4.3042GHz.
Measured DDS Nyquist output spectra zoomed in to 100MHz span
Fig. 10.
and 8.6GHz clock. The enveloped signal frequency is ther mixing of the output
and its image, which is 8.4MHz.
Measured DDS output waveform with 4.2958GHz Nyquist output
maximum clock frequency of 8.6GHz, and an SFDR of 40dBc.
The Power consumption of the DDS is approximately 4.8W,
and the power efficiency FOM is 182GHz·2ENOB/W. This
DDS MMIC is the first mm-wave DDS with larger than 11-bit
phase and 10-bit DAC amplitude resolutions and achieves the
best power efficiency.
ACKNOWLEDGMENT
The authors would like to acknowledge Eric Adler and
Geoffrey Goldman at U.S. Army Research Laboratory and
Pete Kirkland and Rodney Robertson at U.S. Army Space and
Missile Defense Command for funding this project.
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