Conference Paper

Predicting the SEU Error Rate through Fault Injection for a Complex Microprocessor

TIMA Lab., Grenoble
DOI: 10.1109/ISIE.2008.4677290 Conference: Industrial Electronics, 2008. ISIE 2008. IEEE International Symposium on
Source: IEEE Xplore


This paper deals with the prediction of SEU error rate for an application running on a complex processor. Both, radiation ground testing and fault injection, were performed while the selected processor, a Power PC 7448, executed a software issued from a real space application. The predicted error rate shows that generally used strategies, based on static cross-section, significantly overestimate the application error rate.

3 Reads
  • Source
    • "Most works about comparing accelerated radiation and fault injection Single Error Upset (SEU) rate, are based on the underlying memory cross-section [12], or with a low number of error classes. In [13], only 3 classes are given : " CME Errors " being an erroneous result, " Loss sequence " representing an erroneous timing cycle count and " Halted " corresponding to an hardware exception that stops the execution of the program. "
    [Show abstract] [Hide abstract]
    ABSTRACT: In this paper, we present the heavy-ion radiation test results for a 7-stage SPARC micro-processor. Special software handlers enabled fine grained classification of the types of crashes. The measured crash cross sections are compared with those predicted by fault injection simulation.
    2014 IEEE International Reliability Physics Symposium (IRPS); 06/2014
  • Source
    • "An exhaustive fault injection experiment requires executing N SEU runs, each one lasting T clock cycles, and therefore a potentially very long time even in hardware-accelerated setups. As a consequence, fault injection is often performed on a reduced statistical sample of the possible faults [19] [20] [21] [22]. "
    [Show abstract] [Hide abstract]
    ABSTRACT: Nowadays, integrated circuit technologies are increasingly being more susceptible to ionizing radiation effects. In order to assess the reliability of a digital system performing a specific application and to identify the most critical failure effects, radiation experiments and fault injection campaigns are usually performed, which may be costly and time-expensive. This paper proposes a fully automated, practical methodology for accelerating Single-Event-Upset (SEU) fault injection campaigns in digital circuits. The main underlying principle is based on the correlation between the effects of the SEU fault model with the Stuck-At (SA) one. Circuital and functional analysis and experimental case studies confirm the effectiveness of the proposed solutions.
    IEEE Transactions on Industrial Informatics 10/2012; 9(1). DOI:10.1109/TII.2012.2226096 · 8.79 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: The purpose of TAFT fault tolerance studies conducted at CNES is to prepare the space community for the significant evolution linked to the usage of COTS components for developing spacecraft supercomputers. CNES has patented the DMT and DT2 fault-tolerant architectures with 'light' features. The development of a DMT/DT2 testbench based on a PowerPC7448 microprocessor from e2v is presented in this paper.
    On-Line Testing Symposium, 2008. IOLTS '08. 14th IEEE International; 08/2008
Show more