Digitally-enhanced high-order ΔΣ modulators

Abstract

The input feedforward path in a DeltaSigma modulator is an attractive technique for low-distortion swing-reduction design. It helps lower the power dissipation, especially in DeltaSigma modulators designed with low oversampling ratios (OSRs) in low-voltage nanometer CMOS technologies. However, a DeltaSigma modulator with analog feedforward (AFF) requires an analog adder before the quantizer, which can limit the achievable resolution or degrade the signal swing and increase the power dissipation. In this paper, a single-stage multibit DeltaSigma modulator with digital feedforward (DFF) is proposed to realize a high-order finite-impulse-response noise transfer function, thereby achieving high signal-to-quantization-noise ratios at low OSRs. Its key features include reduced swing at the opamp outputs, reduced sensitivity to integrator nonlinearities, and robustness to DeltaSigma modulator coefficient variations, all of which are achieved using only minimal additional digital hardware. Behavioral simulation results confirm that the proposed DFF modulator achieves the swing-reduction and low-distortion performance of an AFF modulator, while eliminating the need for an analog adder.

Full text

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A.A.??   Hamoui,??   M.??   Sukhon,??   F.??   Maloberti:??   "Digitally-­Enhanced??   High-­Order??   ΣΔ??  
Modulators";??  15th??  IEEE??  Int.??  Conf.??  on??  Electronics,??  Circuits??  and??  Systems,??  ICECS??  
2008,??  St.??  Julien's,??  August??  31-­‐September??  3,??  2008,??  pp.??  1115-­‐1118.??  
??  
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Digitally-Enhanced High-Order ΔΣ Modulators
Anas A. Hamoui1, Mohamad Sukhon1, and Franco Maloberti2
1. McGill University, Montreal, Canada (anas.hamoui@mcgill.ca)
2. University of Pavia, Pavia, Italy (franco.maloberti@unipv.it)
Abstract --- The input feedforward path in a ΔΣ modulator is an
attractive technique for low-distortion swing-reduction design.
It helps lower the power dissipation, especially in ΔΣ modulators
designed with low oversampling ratios (OSRs) in low-voltage
nanometer CMOS technologies. However, a ΔΣ modulator with
analog feedforward (AFF) requires an analog adder before the
quantizer, which can limit the achievable resolution or degrade the
signal swing and increase the power dissipation. In this paper, a
single-stage multibit ΔΣ modulator with digital feedforward (DFF) is
proposed to realize a high-order finite-impulse-response noise
transfer function, thereby achieving high signal-to-quantization-noise
ratios at low OSRs. Its key features include reduced swing at the
opamp outputs, reduced sensitivity to integrator nonlinearities, and
robustness to ΔΣ modulator coefficient variations, all of which are
achieved using only minimal additional digital hardware. Behavioral
simulation results confirm that the proposed DFF modulator achieves
the swing-reduction and low-distortion performance of an AFF
modulator, while eliminating the need for an analog adder.
I. INTRODUCTION
of broadband The proliferation digital-communication
applications is stimulating research towards the development of
analog-to-digital converters (ADCs) with higher speeds and higher
resolutions. Potential applications include high-speed wireless
systems, such as 3G and 4G mobile terminals [1]. These high-speed
high-resolution ADCs must be designed in standard digital CMOS
processes to achieve higher system integration and lower fabrication
costs, while harnessing the advanced digital-signal-processing
capabilities of scaled CMOS processes. However, in nanometer
CMOS technologies, the low-power design of high-resolution analog
circuits is complicated by the low supply voltages and the small
devices with poor analog-signal processing capabilities.
Oversampled ΔΣ ADCs are well known for their ability to
achieve high-resolution A/D conversion in low-to-medium speed
applications [2]. However, extending a ΔΣ ADC to broadband
applications requires lowering its oversampling ratio (OSR) in order
for its ΔΣ modulator to be realizable within the technology limitations
of CMOS processes, while meeting a moderate power budget.
Unfortunately, this limits the efficiency of a ΔΣ ADC in achieving
high-resolution A/D conversion.
This paper explores several aspects of the design of high-speed
high-resolution ΔΣ ADCs when the OSR and the supply voltages are
limited by the CMOS technology. Namely:
1) High-Order Multibit ΔΣ Modulator: In a single-stage ΔΣ
modulator (Fig. 1), the loss in signal-to-quantization-noise ratio
(SQNR) due to OSR lowering can be compensated for by increasing
the noise-shaping order of the loop filter
resolution of the internal -bit quantizer [2]. By fully exploiting the
enhanced stability characteristics of multibit quantization (quantizer
overload can be completely avoided [3]), a stable high-order ΔΣ
modulator with an aggressive noise-transfer-functions (NTF) can be
designed to achieve high SQNRs at low OSRs. Thus, the entire noise
budget can be allocated to the analog-noise sources (mainly, thermal
kT/C noise) to reduce the power dissipation.
and/or the
2) Input Feedforward Path: With an input feedforward path
(dashed line in Fig. 1), the analog input signal no longer flows through
the loop filter, but rather reaches the output through the feedforward
path [3]. Since, ideally, the input signal is not processed by the
opamps in the loop-filter integrators, no harmonic distortion is
generated and the signal swing is reduced at the integrator outputs [4].
Hence, the input feedforward path in a ΔΣ modulator is an attractive
technique for low-distortion swing-reduction design. It helps lower
the power dissipation, especially for low-OSR ΔΣ modulators
designed in a low-voltage nanometer CMOS technology [3].
The input feedforward can be implemented using either the
analog feedforward (AFF) path in Fig. 1a or the digital feedforward
(DFF) path in Fig. 1b. An AFF ΔΣ modulator with arbitrary-order
NTF was presented in [3], whereas a DFF ΔΣ modulator with only a
2nd-order NTF was reported in [5].
In this paper, the advantages and design challenges of ΔΣ
modulators with DFF versus AFF paths are outlined. Next, a general
architecture for digitally-enhanced ΔΣ modulators is presented. Then,
to enable the OSR reduction in high-speed ΔΣ ADCs without
compromising the resolution, a multibit ΔΣ modulator with DFF is
proposed to realize finite-impulse-response (FIR) NTFs of arbitrary
orders. Its key features include reduced signal swing at the opamp
outputs, reduced sensitivity to integrator nonlinearities, robustness to
ΔΣ modulator coefficient variations, all of which are achieved using
only minimal additional digital hardware.
NH z ( )
B
E
H(z)
Q2
Yh
X
Y
DAC
(b) Digital-Feedforward (DFF) ΔΣ Modulator
Fig. 1.Linear model of a single-stage ΔΣ modulator with an input
feedforward path (dashed line) implemented in: a) the analog
domain; and b) the digital domain.
B2-bit Quantizer
E
H(z)
Q
Yh
X
B
Y
Xq
DAC
(a) Analog-Feedforward (AFF) ΔΣ Modulator
N-order Loop Filter B-bit Quantizer
Q
B2
B
input feedforward
input feedforward
B
B-bit QuantizerN-order Loop Filter
978-1-4244-2182-4/08/$25.00 ©2008 IEEE. 1115

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This paper is structured as follows: Section II outlines the
advantages and design challenges of DFF versus AFF ΔΣ modulators.
Section III then proposes a multibit DFF ΔΣ modulator with an
arbitrary-order FIR NTF. In Section IV, behavioral simulation results
are presented to compare the performance of the proposed DFF ΔΣ
modulator versus previously-reported AFF ΔΣ modulators.
II. DIGITAL VERSUS ANALOG FEEDFORWARD PATH
A. Analog Implementation
The implementation of an AFF path is complicated by the need
for an analog adder to realize the summation at the quantizer input
(Fig. 1a). This analog adder can be implemented using:
a) an active analog summation amplifier [6]. However, since
this analog amplifier must process the full-scale analog input signal,
the signal swing at the modulator input will be limited by the available
swing at the output of the analog amplifier. Furthermore, the need for
active components (opamps) when using an active amplifier increases
the overall power dissipation.
b) a passive switched-capacitor (SC) network [3]. This
low-power solution is only effective when the number of quantization
bits and, hence, the quantizer input capacitance is small. However, in
the case of multibit quantization, a buffer is needed between the SC
network and the quantizer for proper operation. Furthermore, to
maintain the signal swing at the quantizer input, the quantizer
reference voltage must be scaled down from its nominal value by a
factor equal to the voltage drop across the passive SC network [3].
This also scales down (by the same factor) the quantizer step size and,
hence, the minimum acceptable accuracy (maximum acceptable
offset) for the comparators in the quantizer. Therefore, comparators
with a higher resolution are required.
B. Digital Implementation
To overcome the drawbacks of an analog implementation, the
input feedforward path can be implemented in the digital domain
(Fig. 1b). This requires an extra quantizer. However, owing to the
reduced signal swing with DFF (Section IV), the total number of
comparators required in the main and the extra quantizers of a DFF ΔΣ
modulator is actually smaller than that required in an AFF ΔΣ
modulator with equivalent
Furthermore, although the extra quantizer injects additional
quantization noise at the modulator output, this paper presents a
design technique to cancel at the output of a DFF ΔΣ modulator
(Section III).
noise-shaping characteristics.
III. PROPOSED ΔΣ MODULATOR WITH DFF
A. Proposed Architecture for a ΔΣ Modulator with DFF
Consider the ΔΣ modulator proposed in Fig. 2. Here, the input
feedforward path is implemented in the digital domain. Then, to
cancel the additional quantization noise
ΔΣ modulator, the output of the extra B2-bit quantizer is differentiated
in the digital domain and added to the input of the last integrator in the
ΔΣ loop filter. This results in
output, which cancels the
the modulator output signal is:
at the output of the DFF
appearing at the modulator
injected by the DFF path. Thus,
(1)
whereSignal Transfer Function
Noise Transfer Function
Loop Transfer Function
This is identical to the output of a classical ΔΣ modulator with no
input feedforward (Fig. 1a without the dashed line). However, the
advantage of this DFF ΔΣ modulator is that the signal component at
the output of the loop filter (the input of the main quantizer) is reduced
1
–
–
() X
from
band. Thus, only the 1st derivative of the analog input signal
appears at the output of the last integrator in the ΔΣ loop filter.
Accordingly, the signal swing is reduced at the output of the
loop-filter integrators.
to within the signal
Q
X
Y
Integ N
aN
1z
1
–
–
---------------- -
DAC
1
aN
------- 1z1
–
–
()
z1
–
H1(z)
Q2
Fig. 2.Proposed architecture for a ΔΣ modulator with DFF.
DAC
z
1
–
B2-bit
Quantizer
B-bit
Quantizer
Yh
B2
B
Integ 1 ... (N-1)
Q2
Q2
Q2
XQ2
+
)
(
Q2
)
–
+
X
(
YSTF X
⋅
NTF Q
⋅
+=
STF
H
+
1
+
aN
–
1H
------------ -
=
NTF
1H
------------ -
=
HH1
1z
1
–
--------------- -
=
STF XX
≅⋅
STFz
1z
1
–
–
() X
≅
X
B
z-1
a3
a4
aN
X
Y
Q
∫∫∫∫
Fig. 3.A high-order ΔΣ modulator with AFF and an FIR NTF, presented in [3]. Here, .
11z
1
–
–
()⁄≡
∫
DAC
z-1
∫
z-1
z-1
z-1
Integ 1
Integ N
Na3
3
a4a5a6
3
4 2 + 2z-1
5
6 4 and 2z-19 11 6
4
5 55
1116

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B. High-Order ΔΣ Modulator with DFF
The simplest NTF, which can achieve a high SQNR at low OSRs,
is a high-pass FIR transfer function with zeros at dc:
(2)
To realize an FIR NTF of arbitrary order
modulator shown in Fig. 4 is proposed. This proposed design applies
the DFF design concept shown in Fig. 2 to the AFF ΔΣ modulator
shown in Fig. 3.
, the multibit DFF ΔΣ
IV. BEHAVIORAL SIMULATION RESULTS
A. Behavioral Simulation Conditions and Models
The proposed DFF ΔΣ modulator (Fig. 4) and the previously-
reported AFF ΔΣ modulator (Fig. 3) were simulated in SIMULINK
for the following design specifications:
• 3rd-order NTF (N=3) and OSR = 16
• 32-level mid-tread quantizer (B =5 bits).
• The quantizer reference voltage is normalized to
• The amplitude of the sinusoidal input is
• The input-signal frequency is
the first 4 input-signal harmonics to fall within the signal band.
V.
V (-6 dBFS).
, in order for
)
The SIMULINK behavioral simulations accounted for the
following loop-filter nonidealities:
1) Opamp Nonidealities: The discrete-time loop-filter integrators
are modeled as described in [7] to account for the finite dc gains, the
nonlinear dc-gain variations, and the output saturation voltages of the
opamps in practical switched-capacitor (SC) integrators. These
opamps are assumed to have a maximum dc gain
(43 dB) and an output saturation voltage
account for the low dc gains of the opamps in nanometer CMOS
technologies. In these scaled technologies, opamps with low dc gains
are readily obtainable using classical folded-cascode or current-mirror
designs. However, high-gain opamps require either multiple gain
stages or output-impedance enhancement [8], due to the low supply
voltages and poor intrinsic gains of the MOS transistors in scaled
CMOS technologies. Such gain-boosting techniques for the opamps
significantly increase the power dissipation and degrade the speed.
= 150 V/V
= 1 V. This is to
2) Modulator Coefficients: To account for variations in modulator
coefficients, the signal-to-noise-plus-distortion ratio (SNDR) values
reported correspond to the minimum SNDR values found over 50
simulations in which each modulator coefficient is assumed to have a
uniformly-distributed random error in the range = 1%.
B. Behavioral Simulation Results
Table I summarizes the behavioral simulation results.
Accordingly, the proposed DFF ΔΣ modulator achieves the same
SNDR and output-swing reduction as the previously-reported AFF
ΔΣ modulator. Observe that the signal swing at the quantizer input is
much more reduced in the proposed DFF modulator, compared to the
AFF modulator. This is because the inband signal component at the
quantizer input is approximately
it is only for the proposed DFF modulator (Section III).
1z
–
() X
for the AFF modulator, whereas
z-1
a3
a4
aN
Na3
3
a4
a5
a6
3
4
5
6
2 + 2z-1
5
4 and 2z-1
4
5
9
5
116
1z
1
–
–
X
Y
Q
Q2
∫∫∫∫
Fig. 4.Proposed high-order multibit ΔΣ modulator with DFF.
The feedforward coefficients ak (k = 3, ... , ) needed to realize the FIR NTF in equation (2) are given in the table. Here, .
N 11z
1
–
–
()⁄≡
∫
DAC
z-1
∫
z-1
z-1
DAC
z1
–
z1
–
B bits
B2
B
B
Integ 1
Integ N
B2 bits
N
N
NTF1z
1
–
–
()
=
N
VREF
0.5
1
=
Vin
fS
=
⋅
fin
8 OSR
(⁄
=
A0max
VOsat
ecoeff
±
TABLE I COMPARISON BETWEEN AFF AND DFF ΔΣ MODULATORS
AFF modulator
[7]
(Fig. 3)
N = 3
B = 5 bits
Proposed
DFF modulator
(Fig. 4)
N = 3
B = 5 bits
B2 = 5 bits B2 = 4 bits
SNDR at
with

1st-integrator Output Swing
(absolute maximum)
2nd-integrator Output Swing
(absolute maximum)
3rd-integrator Output Swing
(absolute maximum)
Quantizer Input Swing
(absolute maximum)
No. of Comparators
in Main Quantizer
No. of Comparators
in Extra Quantizer
Total No. of Comparators
dBFS
= 150V/V
= 1%
86.8 dB86.5 dB86.7 dB
0.12 V 0.11 V0.11 V
0.06 V0.09 V0.09 V
0.19 V0.21 V0.23 V
0.67 V0.21 V 0.23 V
3278
032 16
323924
Vin
6
–=
A0max
ecoeff
±
X
1
–
1117

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Thus, in the AFF modulator, the full-swing input signal
the input of the main quantizer and, hence, all comparators in main
quantizer are needed to digitize the input signal. However, in the
proposed DFF modulator, only the 1st derivative of
input of the main quantizer. Owing to this swing reduction (as shown
in Table I), the number of comparators needed in the main quantizer
of the proposed DFF modulator can be reduced from 32 to
. Furthermore, observe that (Table I) the performance
of the proposed DFF modulator is maintained even if the number of
quantization bits in its extra quantizer is reduced from 5 bits
(31 levels) to 4 bits (15 levels). Accordingly, the total number of
comparators required in the main and the extra quantizers of the
proposed DFF modulator is actually smaller than that required in the
AFF modulator.
Figure 5 shows the swing distribution at the output of each
integrator. Accordingly, the swing reduction in the proposed DFF ΔΣ
modulator is comparable to that in the AFF ΔΣ modulator.
Figure 6a depicts the SNDR versus input-signal levels.
Accordingly, the SNDR and dynamic-range performances of the
proposed DFF modulator are similar to that of the AAF modulator.
Figure 6b shows the SNDR versus the maximum dc gain
of the opamps, for a coefficient error
sensitivity of the proposed DFF modulator to nonlinear variations in
opamp dc gains is comparable to that of the AFF modulator.
Furthermore, it can achieve a high resolution and linearity
(SNDR > 13 bits) using opamps with only moderate dc gains (as low
as 60V/V or 36dB), thereby confirming the reduced sensitivity of the
proposed DFF modulator to opamp dc gains.
Figure 6c shows the SNDR versus the error
coefficients, assuming a maximum dc gain
for the opamps. Accordingly, the proposed DFF modulator can
tolerate a 2% variation its loop-filter coefficients with only 1.1 dB
drop in SNDR, thereby confirming the robustness of the proposed
DFF modulator to coefficient variations.
appears at
appears at the
= 1%. Accordingly, the
in the modulator
=150V/V (43dB)
V. CONCLUSION
A high-order multibit ΔΣ modulator with FIR NTF was proposed
to reach high SQNRs at low OSRs. Through digital enhancement
using minimal additional hardware, the proposed ΔΣ modulator
achieves reduced swing at the opamp outputs, reduced sensitivity to
integrator nonlinearities, and robustness to coefficient variations.
Thus, it is particularly suitable for designing high-speed high-
resolution ADCs in low-voltage CMOS technologies.
VI. REFERENCES
[1] A. Rusu, D. Rodriguez de Llera Gonzalez, and M. Ismail,
“Reconfigurable ADCs enable smart radios for 4G wireless connectivity,”
IEEE Circuits and Devices Magazine, vol. 22, pp. 6-11, May/June 2006.
[2] F. Maloberti, Data Converters. Dordrecht, Netherlands: Springer, 2007
[3] A. A. Hamoui and K. Martin, "High-order multibit modulators and
pseudo data-weighted-averaging in low-oversampling ΔΣ ADCs for broad-
band applications," IEEE Trans. Circuits Syst. I, vol. 51, pp. 72-85, Jan.
2004.
[4] J. Silva, U-K Moon, J. Steensgaard, and G. C. Temes, “Wideband low-
distortion delta-sigma ADC topology,” IEE Electron. Lett., vol. 37, pp.
737-738, Jun. 2001.
[5] S. Kwon and F. Maloberti, “A 14mW multi-bit ΔΣ modulator with
82dB SNR and 86dB DR for ADSL2+;” in ISSCC Dig. Tech. Papers, Feb.
2006, pp. 161-170.
[6] K.Y. Nam, S.-M. Lee, D.K. Su, and B. A. Wooley, B.A., “A low-
voltage low-power sigma-delta modulator for broadband analog-to-digital
conversion,” IEEE J. Solid-State Circuits, vol. 40, pp. 1855-1864 Sept.
2005.
[7] A. A. Hamoui et al., “Behavioral modeling of opamp gain and
dynamic effects for power optimization of delta-sigma modulators and
pipelined ADCs,” in Proc. IEEE International Symposium on Low Power
Electronics and Design (ISLPED), Oct. 2006, pp. 330-333.
[8] D. Johns and K. Martin, Analog Integrated Circuit Design. Toronto,
ON: Wiley, 1997.
X
X
320.21
×
7
→
B2
A0max
ecoeff
ecoeff
A0max
−0.2−0.10 0.10.2
0
1
2
3
4
5
6x 10
4
−0.1−0.0500.050.1
0
1
2
3
4
5
6x 10
4
−0.15 −0.1 −0.0500.050.1 0.15
0
2
4
6
8x 10
4
Fig. 5.Signal swing at the integrator outputs. Here: _._ proposed DFF ΔΣ modulator in Fig. 4 (B = 5 bits, B2 = 4 bits); ____ AFF ΔΣ modulator in Fig. 3 [5].
Integrator 3
Integrator 2
Integrator 1
Occurrences
Output Voltage (V)
Occurrences
Output Voltage (V)
Occurrences
Output Voltage (V)
00.511.52
70
75
80
85
90
0204060 80
50
60
70
SNDR (dB)
80
90
−40
-40
−30−20−100
0
20
40
60
80
100
Fig. 6.SNDR versus: a) input-signal level Vin (with A0max = 150V/V and ecoeff = 0); b) opamp’s maximum DC gain A0max (with ecoeff = 1%);
and c) modulator’s coefficient error ecoeff (with A0max = 150V/V).
Here: _._ proposed DFF ΔΣ modulator in Fig. 4 (N = 3, B = 5 bits, B2 = 4bits); ____ AFF ΔΣ Modulator in Fig. 3 [5] (N = 3, B = 5 bits).
SNDR (dB)
SNDR (dB)
SNDR (dB)
ecoeff (%)
(c)
(a)
(b)
0
-20
Vin (dBFS)
A0max (dB)
1118