Two-dimensional crosstalk avoidance codes
ABSTRACT Global buses in deep submicron system-on-chip designs suffer from increasing crosstalk delay as the feature size shrinks. As an technology-independent solution, crosstalk avoidance coding alleviates the problem while requiring less area and power than shielding. Most previously considered crosstalk avoidance codes are one-dimensional, and have limited code rates. In this paper, we propose two-dimensional crosstalk avoidance codes (TDCAC), which achieve higher code rate at the expense of longer latency. Specifically, we investigate the maximum code rate for TDCAC with and without memory.
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ABSTRACT: As process technologies scale into deep submicrometer region, crosstalk delay is becoming increasingly severe, especially for global on-chip buses. To cope with this problem, accurate delay models of coupled interconnects are needed. In particular, delay models based on analytical approaches are desirable, because they are not only largely transparent to technology, but also explicitly establish the connections between delays of coupled interconnects and transition patterns, thereby enabling crosstalk alleviating techniques such as crosstalk avoidance codes. Unfortunately, existing analytical delay models, such as the widely cited model in , have limited accuracy and do not account for loading capacitance. In this brief, we propose analytical delay models for coupled interconnects that address these disadvantages.IEEE Transactions on Very Large Scale Integration (VLSI) Systems 07/2014; 22(7):1639-1644. DOI:10.1109/TVLSI.2013.2275071 · 1.14 Impact Factor
Article: Beware the Dynamic C-Element[Show abstract] [Hide abstract]
ABSTRACT: The C-element is a well known component of asynchronous circuits. To overcome problems of current CMOS technologies, its use has even been extended to specific domains of the synchronous paradigm, such as clock generation, clock gating, and registers. An economical implementation of this component is the dynamic C-element. Its advantages over static implementations are reduced power, transition, and propagation delays as well as lower silicon area. Yet, research evaluating its electrical behavior, functionality, and robustness is scarce. This brief presents an in-depth analysis of the dynamic C-element electrical behavior. The analysis points to a constrained nature, which can lead to undefined output logic values, as well as excessive static power consumption. The brief also proposes a technique for robust design of such components that avoids such undefined values.IEEE Transactions on Very Large Scale Integration (VLSI) Systems 07/2014; 22(7):1644-1647. DOI:10.1109/TVLSI.2013.2276538 · 1.14 Impact Factor
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ABSTRACT: Achieving reliable operation under the influence of deep-submicrometer noise sources including crosstalk noise at low voltage operation is a major challenge for network on chip links. In this paper, we propose a coding scheme that simultaneously addresses crosstalk effects on signal delay and detects up to seven random errors through wire duplication and simple parity checks calculated over the rows and columns of the two-dimensional data. This high error detection capability enables the reduction of operating voltage on the wire leading to energy saving. The results show that the proposed scheme reduces the energy consumption up to 53% as compared to other schemes at iso-reliability performance despite the increase in the overhead number of wires. In addition, it has small penalty on the network performance, represented by the average latency and comparable codec area overhead to other schemes.Circuits and Systems I: Regular Papers, IEEE Transactions on 07/2014; 61(7):2034-2047. DOI:10.1109/TCSI.2013.2295952 · 2.30 Impact Factor