Two-dimensional crosstalk avoidance codes
ABSTRACT Global buses in deep submicron system-on-chip designs suffer from increasing crosstalk delay as the feature size shrinks. As an technology-independent solution, crosstalk avoidance coding alleviates the problem while requiring less area and power than shielding. Most previously considered crosstalk avoidance codes are one-dimensional, and have limited code rates. In this paper, we propose two-dimensional crosstalk avoidance codes (TDCAC), which achieve higher code rate at the expense of longer latency. Specifically, we investigate the maximum code rate for TDCAC with and without memory.
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- "To further improve the coding rate, two-dimensional forbidden transition codes with block length larger than 1 were proposed in , and it was shown that the coding rate could be increased to more than 80%. However, no explicit constructions of such codes (and the associated encoders/decoders) were given in . Our main contribution in this paper is to propose a simple bit-stuffing algorithm for generating forbidden transition codes and develop its associated analysis. "
ABSTRACT: Motivated by the design of high speed switching fabrics, in this paper we propose a bit-stuffing algorithm for generating forbidden transition codes to mitigate the crosstalk effect between adjacent wires in long on-chip buses. We first model a bus with forbidden transition constraints as a forbidden transition channel, and derive the Shannon capacity of such a channel. Then we perform a worst case analysis and a probabilistic analysis for the bit-stuffing algorithm. We show by both theoretic analysis and simulations that the coding rate of the bit stuffing encoding scheme for independent and identically distributed (i.i.d.) Bernoulli input traffic is quite close to the Shannon capacity, and hence is much better than those of the existing forbidden transition codes in the literature, including the Fibonacci representation.INFOCOM 2010. 29th IEEE International Conference on Computer Communications, Joint Conference of the IEEE Computer and Communications Societies, 15-19 March 2010, San Diego, CA, USA; 01/2010
Conference Paper: A Convolutional Code for On-chip Interconnect Crosstalk Reduction[Show abstract] [Hide abstract]
ABSTRACT: Interconnects are now considered as the bottleneck in the design of system-on-chip (SoC) since they introduce delay and power consumption. To deal with this issue, data-coding for interconnect power and timing optimization is a promising method. Based on some realistic observations on interconnect delay and power estimation, a new data-coding technique called ldquoConvolutional Encoder for Crosstalk Reductionrdquo (CECR) is proposed. It allows the reduction of delay, power consumption (including extra power consumption due to codecs) and noise for on-chip buses. The concept of the technique is to reduce the switching activity to its minimum considering the transmission of data on the encoded wires. Results show the technique efficiency for different technologies and bus lengths. The power consumption reduction can reach up to 12% for a 10 mm bus in the 65 nm technology and more if buses are longer. It also allows the acceleration of the data propagation of 20% and the reduction of the overall worst noise case transitions of 51%.International Symposium on Circuits and Systems (ISCAS 2009), 24-17 May 2009, Taipei, Taiwan; 05/2009
Conference Paper: Improved analytical delay models for coupled interconnects.[Show abstract] [Hide abstract]
ABSTRACT: With the advance of the process technologies into deep sub-micrometer domain, crosstalk between adjacent wires of global interconnects has become more severe. The delay caused by the crosstalk becomes a bottleneck to system performance, especially those with global interconnects. To alleviate crosstalk delays, accurate delay models are needed. In particular, analytical models are more desirable for their simplicity and transparency to technology, which lead to efficient crosstalk avoidance code (CAC) designs. Currently, most existing CAC designs are based on the analytical model proposed by Sotiriadis et al., which has limited accuracy. In this paper, we propose new analytical delay models, and our extensive simulations show that they have improved accuracy.Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2011, October 4-7, 2011, Beirut, Lebanon; 01/2011